Message ID | 20181220163123.9233-1-mark.cave-ayland@ilande.co.uk |
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Headers | show
Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43LHNh4wS6z9s3q for <incoming@patchwork.ozlabs.org>; Fri, 21 Dec 2018 03:32:36 +1100 (AEDT) Received: from localhost ([::1]:38556 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>) id 1ga1FS-0007po-C6 for incoming@patchwork.ozlabs.org; Thu, 20 Dec 2018 11:32:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <mark.cave-ayland@ilande.co.uk>) id 1ga1Ef-0007pa-Gz for qemu-devel@nongnu.org; Thu, 20 Dec 2018 11:31:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from <mark.cave-ayland@ilande.co.uk>) id 1ga1Eb-0000hu-GD for qemu-devel@nongnu.org; Thu, 20 Dec 2018 11:31:45 -0500 Received: from chuckie.co.uk ([82.165.15.123]:37271 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from <mark.cave-ayland@ilande.co.uk>) id 1ga1Eb-0000V1-78; Thu, 20 Dec 2018 11:31:41 -0500 Received: from host86-177-178-114.range86-177.btcentralplus.com ([86.177.178.114] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from <mark.cave-ayland@ilande.co.uk>) id 1ga1Ei-0000iB-N4; Thu, 20 Dec 2018 16:31:49 +0000 From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, richard.henderson@linaro.org, david@gibson.dropbear.id.au Date: Thu, 20 Dec 2018 16:31:14 +0000 Message-Id: <20181220163123.9233-1-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 X-SA-Exim-Connect-IP: 86.177.178.114 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH v3 0/9] target/ppc: prepare for conversion to TCG vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
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target/ppc: prepare for conversion to TCG vector operations
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This patchset is an attempt at trying to improve the VMX (Altivec) instruction performance by laying the groundwork for use of the new TCG vector operations. Patches 1 and 2 fix a sign-extension error discovered in EXTRACT_SHELPER and an associated typo in the SIMM5 macro which were discovered whilst testing Richard's follow-on TCG vector improvements patchset. In order to use TCG vector operations, the registers must be accessible from cpu_env whilst currently they are accessed via arrays of static TCG globals. Patches 3-5 are therefore mechanical patches which introduce access helpers for FPR, AVR and VSR registers using the supplied TCGv_i64 parameter. Once this is done, patch 6 enables us to remove the static TCG global arrays and updates the access helpers to read/write to the relevant fields in cpu_env directly. Patches 7 and 8 perform the legwork required to enable VSX instructions to be converted to use TCG vector operations in future by rearranging the FP, VMX and VSX registers into a single aligned VSR register array (the scope of this patchset is VMX only). Patch 9 removes the AVR* macros and replaces them with the corresponding Vsr* macros since they are equivalent. Finally thanks to Richard for taking the time to answer some of my (mostly beginner) questions related to TCG. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> v3: - Rebase onto master, drop RFC prefix, alter subject line - Add A-B tags from David - Add SIMM5/EXTRACT_HELPER macro fix patches to the start of the series - Drop patch 4 from previous patchset (delay AVR register writeback) as it should not be required. - Remove extra get_fpr() accidentally added to GEN_FLOAT macros in patch 3 - Fix temporary leak when VMX/VSX not enabled in patches 4 and 5 - Add patch to remove AVR* macros, replacing them with Vsr* macros - Drop patches converting logical, add and sub instructions to TCG vector ops (let Richard incorporate this into his TCG vector improvements patchset) v2: - Rebase onto master - Add comment explaining rationale for FPR helpers in description for patch 1 - Add R-B tags from Richard - Add patch 3 to delay AVR register writeback as spotted by Richard - Add patches 6 and 7 to merge FPR, VMX and VSX registers into the vsr array to facilitate conversion of VSX instructions to vector operations later - Fix accidental bug whereby the conversion of get_vsr()/set_vsr() to access data from cpu_env was incorrectly squashed into patch 3 - Move set_fpr() further down in gen_fsqrts() and gen_frsqrtes() in patch 1 Mark Cave-Ayland (9): target/ppc: fix typo in SIMM5 extraction helper target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extract32 target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register access target/ppc: introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env target/ppc: merge ppc_vsr_t and ppc_avr_t union types target/ppc: move FP and VMX registers into aligned vsr register array target/ppc: replace AVR* macros with Vsr* macros linux-user/ppc/signal.c | 24 +- target/ppc/arch_dump.c | 12 +- target/ppc/cpu.h | 26 +- target/ppc/gdbstub.c | 8 +- target/ppc/int_helper.c | 94 ++-- target/ppc/internal.h | 43 +- target/ppc/machine.c | 72 ++- target/ppc/monitor.c | 4 +- target/ppc/translate.c | 73 ++- target/ppc/translate/dfp-impl.inc.c | 2 +- target/ppc/translate/fp-impl.inc.c | 486 +++++++++++++++----- target/ppc/translate/vmx-impl.inc.c | 154 +++++-- target/ppc/translate/vsx-impl.inc.c | 862 ++++++++++++++++++++++++++---------- target/ppc/translate_init.inc.c | 24 +- 14 files changed, 1339 insertions(+), 545 deletions(-)