From patchwork Thu Apr 28 03:37:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~eopxd X-Patchwork-Id: 1623396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KphCj3d8hz9sBy for ; Thu, 28 Apr 2022 13:38:09 +1000 (AEST) Received: from localhost ([::1]:33788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1njuyl-0001QE-A3 for incoming@patchwork.ozlabs.org; Wed, 27 Apr 2022 23:38:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njuxp-0001GA-DJ; Wed, 27 Apr 2022 23:37:09 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:42326) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njuxm-0002mG-2q; Wed, 27 Apr 2022 23:37:09 -0400 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 0FB6C11EEFE; Thu, 28 Apr 2022 03:37:03 +0000 (UTC) From: ~eopxd Date: Thu, 28 Apr 2022 03:37:02 +0000 MIME-Version: 1.0 Subject: [PATCH qemu v11 00/15] Add tail agnostic behavior for rvv instructions Message-ID: <165111702275.848.16529145411603891061-0@git.sr.ht> X-Mailer: git.sr.ht To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to enable the behavior, it is default as disabled. There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between tail policies. Setting agnostic elements to all 1s makes things simple and allow QEMU to express this. We may explore other possibility of agnostic behavior by adding other options in the future. Please understand that this patch-set is limited. v2 updates: - Addressed comments from Weiwei Li - Added commit tail agnostic on load / store instructions (which I forgot to include into the patch-set) v3 updates: - Missed the very 1st commit, adding it back v4 updates: - Renamed vlmax to total_elems - Deal with tail element when vl_eq_vlmax == true v5 updates: - Let `vext_get_total_elems` take `desc` and `esz` - Utilize `simd_maxsz(desc)` to get `vlenb` - Fix alignments to code v6 updates: - Fix `vext_get_total_elems` v7 updates: - Reuse `max_elems` for vector load / store helper functions. The translation sets desc's `lmul` to `min(1, lmul)`, making `vext_max_elems` equivalent to `vext_get_total_elems`. v8 updates: - Simplify `vext_set_elems_1s`, don't need `vext_set_elems_1s_fns` - Fix `vext_get_total_elems`, it should derive upon EMUL instead of LMUL v9 updates: - Let instructions that is tail agnostic regardless of vta respect the option and not the vta. v10 updates: - Correct range to set element to 1s for load instructions v11 updates: - Separate addition of option 'rvv_ta_all_1s' as a new (last) commit - Add description to show intent of the option in first commit for the optional tail agnostic behavior - Tag WeiWei as Reviewed-by for all commits - Tag Alistair as Reviewed-by for commit 01, 02 - Tag Alistair as Acked-by for commit 03 eopXD (15): target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed target/riscv: rvv: Rename ambiguous esz target/riscv: rvv: Early exit when vstart >= vl target/riscv: rvv: Add tail agnostic for vv instructions target/riscv: rvv: Add tail agnostic for vector load / store instructions target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions target/riscv: rvv: Add tail agnostic for vector integer shift instructions target/riscv: rvv: Add tail agnostic for vector integer comparison instructions target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions target/riscv: rvv: Add tail agnostic for vector floating-point instructions target/riscv: rvv: Add tail agnostic for vector reduction instructions target/riscv: rvv: Add tail agnostic for vector mask instructions target/riscv: rvv: Add tail agnostic for vector permutation instructions target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 + target/riscv/cpu_helper.c | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 176 +++ target/riscv/internals.h | 6 +- target/riscv/translate.c | 4 + target/riscv/vector_helper.c | 1536 ++++++++++++++--------- 7 files changed, 1110 insertions(+), 617 deletions(-)