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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id 9sm5031887pjs.1.2020.10.27.22.30.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Oct 2020 22:30:19 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 00/10] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Date: Wed, 28 Oct 2020 13:30:00 +0800 Message-Id: <1603863010-15807-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Atish Patra , Anup Patel , Ivan Griffin Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the DDR memory controller is not modeled, hence the factory HSS firmware does not boot out of the box on QEMU. A modified HSS is required per the instructions on [1]. This series adds the missing DDR memory controller support to PolarFire SoC, as well as adding various misc models to support the DDR memory initialization done by HSS. With this series, the unmodified HSS image can boot on QEMU out of the box. The latest SD card image [2] released by Microchip was used for testing which includes the pre-built U-Boot, device tree blob and Linux kernel. The instructions on [1] have been updated to latest information. [1] https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit [2] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz Changes in v2: - new patch: Document where to look at the PolarFire SoC memory maps - change to map the reserved memory at address 0 instead of debug memory - Increase the default memory size to 2 GiB Bin Meng (10): hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Hook the I2C1 controller MAINTAINERS | 6 + hw/misc/Kconfig | 9 ++ hw/misc/mchp_pfsoc_dmc.c | 216 ++++++++++++++++++++++++++++++++ hw/misc/mchp_pfsoc_ioscb.c | 242 ++++++++++++++++++++++++++++++++++++ hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++ hw/misc/meson.build | 3 + hw/riscv/Kconfig | 3 + hw/riscv/microchip_pfsoc.c | 123 +++++++++++++++--- include/hw/misc/mchp_pfsoc_dmc.h | 56 +++++++++ include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++++ include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++ include/hw/riscv/microchip_pfsoc.h | 18 ++- 12 files changed, 847 insertions(+), 17 deletions(-) create mode 100644 hw/misc/mchp_pfsoc_dmc.c create mode 100644 hw/misc/mchp_pfsoc_ioscb.c create mode 100644 hw/misc/mchp_pfsoc_sysreg.c create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h