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Tue, 12 May 2020 18:40:23 +0530 (IST) From: Sai Pavan Boddu To: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Jason Wang , Markus Armbruster , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Tong Ho , Ramon Fried Subject: [PATCH v4 00/12] Cadence GEM Fixes Date: Tue, 12 May 2020 18:39:55 +0530 Message-Id: <1589289007-23629-1-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFTY:; SFS:(39860400002)(376002)(346002)(396003)(136003)(46966005)(33430700001)(110136005)(8676002)(26005)(6266002)(478600001)(42186006)(316002)(4326008)(426003)(186003)(2616005)(82310400002)(8936002)(81166007)(36756003)(47076004)(356005)(70586007)(2906002)(33440700001)(5660300002)(70206006)(82740400003)(336012)(6666004); DIR:OUT; SFP:1101; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1ddb9a21-04cd-4e63-b64c-08d7f676f5d7 X-MS-TrafficTypeDiagnostic: DM6PR02MB4332: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-Forefront-PRVS: 0401647B7F X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wMb0MyNloREmBeDEXYCWOtDDfhSQ+N1MnwDISp34xtpvSn2MIEbe7Dmt/YgTqRJoVvANqiJor8aroMGT/mMqZT4+jRR1F9P4UilFX+5D3KKmh3CbLectkozbwszvVpUsarhCtMKD6qYlZbwhHajqWC2QQvgCkuy/why+KHU1m1PYrR1yNm9zVXJokAD/mP/R08GjdX8SsIW5x6OX7Fs5FVRiKZxrYQp3P0MMrTWJRBBiCIOh3ksXr9uDYMu6EbqkJPo/cE910fK1QuAUpGXAYl82fye64DSzTRXSnyDs8CQ4m6EAM1Xy0r83oy20UsgklhV54+WJdHGx1WpiGf8Ldta0+WjLOx5Q+913bI9CyZRvbGvSWsxop0AYVo8wqAMiBQH4hnsvQ+UfyP4IlR1S0MPxqtKnXO6N4ijxKyJuiJrBVp8J9eagq37FcJWqzA5veg3/dFFFQEplv2tY6LDbCKtensyCr1Aa88n+/3uovf8RXCdLeh0FxkvDt+LhbG1Txmol2PXrdI3+PMNWeWqaBd7qWYcp3m3KCO7stcLLDZuMgiPPRwJcsGylXxnmAQjO1CZONvHZecpVB7xiq1sj2g== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2020 13:18:28.7203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ddb9a21-04cd-4e63-b64c-08d7f676f5d7 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4332 Received-SPF: pass client-ip=40.107.94.64; envelope-from=saipava@xilinx.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/12 09:18:31 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Hi, Following patch series fixes issues with priority queues, Adds JUMBO Frame support, Makes Debug statements compilable & Fixes related to multicast frames. Changes for V2: Fixed build failure on fedora docker machine Fix buggy debug print to use sized integer casting Changes for V3: 1/10: Fixed debug statments to use %u and %zd Remove rxoffset for buffer address 2/10: Add inline functions to get tx/rx queue base address. 4/10: fix read only mask 5/10: Move packet buffers to CadenceGEMState 6/10: Add JUMBO MAX LEN register Changes for V4: 7/11: Fix up the existing code style in register defines 8/11: jumbo-max-len property sets the default value of jumbo frame Add frame lenght checks for tx and rx Sai Pavan Boddu (11): net: cadence_gem: Fix debug statements net: cadence_gem: Fix the queue address update during wrap around net: cadence_gem: Fix irq update w.r.t queue net: cadence_gem: Define access permission for interrupt registers net: cadence_gem: Set ISR according to queue in use net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState net: cadence_gem: Fix up code style net: cadence_gem: Add support for jumbo frames net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg net: cadence_gem: Update the reset value for interrupt mask register net: cadence_gem: TX_LAST bit should be set by guest Tong Ho (1): net: cadence_gem: Fix RX address filtering hw/net/cadence_gem.c | 453 ++++++++++++++++++++++++------------------- include/hw/net/cadence_gem.h | 6 + 2 files changed, 260 insertions(+), 199 deletions(-)