| Message ID | 1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com |
|---|---|
| Headers | show |
| Series | target/mips: Update Inter-Thread Communication Unit support | expand |
Patchew URL: https://patchew.org/QEMU/1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=14
=== TEST SCRIPT END ===
CC crypto/hash.o
CC crypto/hash-nettle.o
/tmp/qemu-test/src/block/sheepdog.c: In function 'find_vdi_name':
/tmp/qemu-test/src/block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation]
strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
The full log is available at
http://patchew.org/logs/1546533252-26601-1-git-send-email-aleksandar.markovic@rt-rk.com/testing.docker-mingw@fedora/?type=message.
---
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From: Aleksandar Markovic <amarkovic@wavecomp.com> Inter-Thread Communication Unit (or ITU) represents and important part of contemporary MIPS cores. This series extends support for ITU in QEMU. The changes will not be visible for end users immediatelly, but there are plans to enable corresponding features for certain CPUs soon. Break down by patches: - patches 1-3 are cosmetic improvements of CP0-related definitions - patches 4-5 introduce SAARI and SAAR CP0 registers - patch 6 introduce ITU control register ICR0 - patch 7 add usage of SAARI and SAAR registers within ITU - patch 8 adds handling of bus errors within ITU Aleksandar Markovic (3): target/mips: Move comment containing summary of CP0 registers target/mips: Add preprocessor constants for 32 major CP0 registers target/mips: Use preprocessor constants for 32 major CP0 registers Yongbok Kim (5): target/mips: Add fields for SAARI and SAAR CP0 registers target/mips: Provide R/W access to SAARI and SAAR CP0 registers target/mips: Add field and R/W access to ITU control register ICR0 target/mips: Update ITU to utilize SAARI and SAAR CP0 registers target/mips: Update ITU to handle bus errors hw/mips/cps.c | 8 ++ hw/misc/mips_itu.c | 72 +++++++++- include/hw/misc/mips_itu.h | 8 ++ target/mips/cpu.h | 213 +++++++++++++++++----------- target/mips/helper.h | 6 + target/mips/internal.h | 1 + target/mips/machine.c | 6 +- target/mips/op_helper.c | 64 +++++++++ target/mips/translate.c | 338 ++++++++++++++++++++++++++------------------- 9 files changed, 484 insertions(+), 232 deletions(-)