From patchwork Fri Nov 9 11:49:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Zhang X-Patchwork-Id: 995472 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42rz6W2Yc0z9sC7 for ; Fri, 9 Nov 2018 22:52:33 +1100 (AEDT) Received: from localhost ([::1]:33400 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gL5Kw-0004XG-9i for incoming@patchwork.ozlabs.org; Fri, 09 Nov 2018 06:52:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53744) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gL5KQ-0004Wu-0b for qemu-devel@nongnu.org; Fri, 09 Nov 2018 06:51:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gL5KM-0006zM-N7 for qemu-devel@nongnu.org; Fri, 09 Nov 2018 06:51:57 -0500 Received: from mga05.intel.com ([192.55.52.43]:56441) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gL5KM-0006rm-Dm for qemu-devel@nongnu.org; Fri, 09 Nov 2018 06:51:54 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Nov 2018 03:51:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,483,1534834800"; d="scan'208";a="94993229" Received: from zhangyu-optiplex-9020.bj.intel.com ([10.238.135.159]) by FMSMGA003.fm.intel.com with ESMTP; 09 Nov 2018 03:51:50 -0800 From: Yu Zhang To: qemu-devel@nongnu.org Date: Fri, 9 Nov 2018 19:49:44 +0800 Message-Id: <1541764187-10732-1-git-send-email-yu.c.zhang@linux.intel.com> X-Mailer: git-send-email 1.9.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH v1 0/3] intel-iommu: add support for 5-level virtual IOMMU. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , Peter Xu , Paolo Bonzini , Igor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Intel's upcoming processors will extend maximum linear address width to 57 bits, and introduce 5-level paging for CPU. Meanwhile, the platform will also extend the maximum guest address width for IOMMU to 57 bits, thus introducing the 5-level paging for 2nd level translation(See chapter 3 in Intel Virtualization Technology for Directed I/O). This patch set extends the current logic to support a wider address width. A 5-level paging capable IOMMU(for 2nd level translation) can be rendered with configuration "device intel-iommu,x-aw-bits=57". Yu Zhang (3): intel-iommu: differentiate host address width from IOVA address width. intel-iommu: extend VTD emulation to allow 57-bit IOVA address width. intel-iommu: search iotlb for levels supported by the address width. --- Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Cc: Marcel Apfelbaum Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Peter Xu hw/i386/acpi-build.c | 2 +- hw/i386/intel_iommu.c | 101 +++++++++++++++++++++++++++-------------- hw/i386/intel_iommu_internal.h | 13 ++++-- include/hw/i386/intel_iommu.h | 10 ++-- 4 files changed, 83 insertions(+), 43 deletions(-)