From patchwork Fri Dec 1 18:44:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 843714 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ypQWf6fPfz9sNd for ; Sat, 2 Dec 2017 07:15:58 +1100 (AEDT) Received: from localhost ([::1]:60616 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eKrj2-0007Yj-Qu for incoming@patchwork.ozlabs.org; Fri, 01 Dec 2017 15:15:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55229) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eKqNB-0001tg-1A for qemu-devel@nongnu.org; Fri, 01 Dec 2017 13:49:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eKqNA-0005mp-50 for qemu-devel@nongnu.org; Fri, 01 Dec 2017 13:49:17 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38674) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eKqN4-0005ir-QF; Fri, 01 Dec 2017 13:49:10 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eKqIi-00076c-B7; Fri, 01 Dec 2017 18:44:40 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 1 Dec 2017 18:44:32 +0000 Message-Id: <1512153879-5291-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 0/7] armv8m: Implement TT, and other bugfixes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The main aim of this patchseries is to implement the new-for-v8M TT/TTT/TTA/TTAT instructions (which take an address and do an MPU/SAU lookup and tell you the security state and access permissions for the address). The first part of the series is some smaller bugfixes that I noticed along the way, followed by a bit of refactoring before finally implementing TT in the last patch. (Notably, patch 4 splits the existing MNegPri and MSNegPri MMU indexes into two new indexes each -- when I originally added them I hadn't realized that "negative execution priority" was orthogonal to "user vs privileged", rather than implying privileged. This brings us up to 8 MMU indexes, but that should not cost us any more than having 7, so it seems a better approach than a more convoluted other option (which you can find briefly described in the patch 4 commit message). thanks -- PMM Peter Maydell (7): target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode target/arm: Add missing M profile case to regime_is_user() target/arm: Split M profile MNegPri mmu index into user and priv target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv() target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8() target/arm: Implement TT instruction target/arm/cpu.h | 68 ++++++++----- target/arm/helper.h | 2 + target/arm/internals.h | 6 +- target/arm/helper.c | 268 +++++++++++++++++++++++++++++++++++++------------ target/arm/translate.c | 37 ++++++- 5 files changed, 289 insertions(+), 92 deletions(-)