@@ -35,13 +35,23 @@
static void _i2c_write(struct i2cm *i2cm, uint32_t addr, uint32_t data)
{
- fsi_write(&i2cm->target, addr, data);
- printf("writing 0x%16" PRIx64 "\n", (uint64_t)data << 32);
+ if (i2cm->host) {
+ pib_write(&i2cm->target, addr + I2C_PIB_OFFSET, (uint64_t)data << 32);
+ PR_INFO("\t writing 0x%16" PRIx64 "\n", (uint64_t)data << 32);
+ } else
+ fsi_write(&i2cm->target, addr, data);
}
static void _i2c_read(struct i2cm *i2cm, uint32_t addr, uint32_t *data)
{
- fsi_read(&i2cm->target, addr, data);
+ uint64_t d = (uint64_t)*data;
+
+ if (i2cm->host) {
+ pib_read(&i2cm->target, addr + I2C_PIB_OFFSET, &d);
+ *data = d >> 32;
+ } else {
+ fsi_read(&i2cm->target, addr, data);
+ }
}
static void debug_print_reg(struct i2cm *i2cm)
@@ -166,7 +176,10 @@ static int i2c_poll_status(struct i2cm *i2cm, uint32_t *data)
static int i2c_fifo_write_byte(struct i2cm *i2cm, uint8_t data)
{
PR_INFO("\twriting: %x to FIFO\n", data);
- _i2c_write(i2cm, I2C_FIFO_REG, data);
+ if (i2cm->host)
+ _i2c_write(i2cm, I2C_PIB_FIFO4_REG - I2C_PIB_OFFSET , data);
+ else
+ _i2c_write(i2cm, I2C_FIFO_REG, data);
return 0;
}
@@ -176,6 +189,8 @@ static int i2c_fifo_read_byte(struct i2cm *i2cm, uint8_t *data)
uint32_t tmp = 0xeeeeeeee;
_i2c_read(i2cm, I2C_FIFO_REG, &tmp);
+ if (i2cm->host)
+ tmp = tmp >> 24;
PR_INFO("\tread byte: %x \n", tmp);
if (tmp == 0xeeeeeeee)
return 1;
@@ -342,9 +357,124 @@ static struct i2cm i2c_fsi = {
.probe = i2cm_target_probe,
},
.read = i2c_get,
+ .host = false
};
DECLARE_HW_UNIT(i2c_fsi);
+
+/////////////////////////////////////////////////////////////////////////////
+#define I2C_ATOMIC_LOCK_REG 0x3ff
+#define OCC_BASE 0x00000000006C08A
+#define OCC_CLEAR 0x00000000006C08B
+#define OCC_SET 0x00000000006C08C
+
+
+#define OCC_LOCKED_ENGINE_1 PPC_BIT(17)
+#define OCC_LOCKED_ENGINE_2 PPC_BIT(19)
+#define OCC_LOCKED_ENGINE_3 PPC_BIT(21)
+#define I2CM_DT_TO_ID(x) ((x>>12) & 0xf)
+static int i2cm_locked_by_occ(int id, uint64_t occ_base)
+{
+ uint64_t mask;
+ switch (id)
+ {
+ case 1:
+ mask = OCC_LOCKED_ENGINE_1;
+ break;
+ case 2:
+ mask = OCC_LOCKED_ENGINE_2;
+ break;
+ case 3:
+ mask = OCC_LOCKED_ENGINE_3;
+ break;
+ default:
+ mask = 0;
+ break;
+ }
+ return !!(mask & occ_base);
+}
+
+static int pib_i2c_get(struct i2cm *i2cm, uint16_t port, uint32_t addr, uint32_t offset, uint16_t size, uint64_t *d)
+{
+ uint64_t data = 0;
+ int dt_id = pdbg_target_address(&i2cm->target, NULL);
+ int id = I2CM_DT_TO_ID(dt_id);
+ uint64_t bit = PPC_BIT(16 + (id - 1) * 2);
+ /*
+ * 1 0x800000000000
+ * 2 0x200000000000
+ * 3 0x080000000000
+ * */
+ struct pdbg_target *p;
+ data = 0xdedddeaddeaddead;
+ pdbg_for_each_class_target("pib", p) {
+ if (pdbg_target_probe(p) == PDBG_TARGET_ENABLED)
+ break;
+ }
+
+ if (!p) {
+ fprintf(stderr, "No PIB found\n");
+ return 0;
+ }
+ pib_read(p, OCC_BASE, &data);
+ PR_INFO("I2C: engine%d: occflags = 0x%16" PRIx64 "%x %x %x(locks = %x:%x:%x)\n",
+ id, (u64) data,
+ (u32) GETFIELD(PPC_BIT(17), data),
+ (u32) GETFIELD(PPC_BIT(19), data),
+ (u32) GETFIELD(PPC_BIT(21), data),
+ (u32) GETFIELD(PPC_BITMASK(16, 17), data),
+ (u32) GETFIELD(PPC_BITMASK(18, 19), data),
+ (u32) GETFIELD(PPC_BITMASK(20, 21), data));
+
+ if( !i2cm_locked_by_occ(id, data)) {
+ /* lock i2cm */
+ pib_write(p, OCC_SET, bit);
+ pib_read(p, OCC_BASE, &data);
+
+ // read status
+ pib_read(&i2cm->target, I2C_STATUS_REG + I2C_PIB_OFFSET, &data);
+ PR_INFO("\n## status 0x%16" PRIx64"\n", data);
+ i2c_get(i2cm, port, addr, offset, size, d);
+
+ /* unlock i2cm */
+ pib_read(p, OCC_BASE, &data);
+ pib_read(p, OCC_CLEAR, &data);
+ pib_write(p, OCC_CLEAR, bit);
+ pib_read(p, OCC_BASE, &data);
+ PR_INFO("I2C: de%d: occflags = 0x%16" PRIx64 "(locks = %x:%x:%x)\n",
+ id, (u64) data, (u16) GETFIELD(PPC_BITMASK(16, 17), data),
+ (u16) GETFIELD(PPC_BITMASK(18, 19), data),
+ (u16) GETFIELD(PPC_BITMASK(20, 21), data));
+ }
+ else
+ PR_INFO("I2C master %x is locked by OCC :( \n", id);
+
+ return 0;
+}
+
+int host_i2cm_target_probe(struct pdbg_target *target)
+{
+#define FSI_SET_PIB_RESET_REG 0x07
+
+ CHECK_ERR(fsi_write(target, FSI_SET_PIB_RESET_REG, 1));
+// struct pib *pib = target_to_pib(target);
+
+ // should we confirm that we can reach the i2c master here?
+
+ return 0;
+}
+
+static struct i2cm i2c_pib = {
+ .target = {
+ .name = "PIB I2C Master",
+ .compatible = "ibm,power9-i2cm",
+ .class = "i2cm",
+ .probe = i2cm_target_probe,
+ },
+ .read = pib_i2c_get,
+ .host = true,
+};
+DECLARE_HW_UNIT(i2c_pib);
/////////////////////////////////////////////////////////////////////////////
#ifndef DISABLE_I2CLIB
@@ -18,7 +18,11 @@
#include "bitutils.h"
-/* I2C common registers */
+/*
+ * I2C common registers
+ * - use as is on CFAM
+ * - use with I2C_PIB_OFFSET on PIB
+ */
#define I2C_FIFO_REG 0x0
#define I2C_CMD_REG 0x1
#define I2C_MODE_REG 0x2
@@ -32,11 +36,13 @@
#define I2C_RESIDUAL_REG 0x9
#define I2C_PORT_BUSY_REG 0xA
+/* I2C PIB only */
#define I2C_PIB_OFFSET 0x4
#define I2C_PIB_ENGINE_0 0x0000
#define I2C_PIB_ENGINE_1 0x1000
#define I2C_PIB_ENGINE_2 0x2000
#define I2C_PIB_ENGINE_3 0x3000
+#define I2C_PIB_FIFO4_REG 0x12
/* I2C command register bits */
#define I2C_CMD_WITH_START PPC_BIT32(0)
@@ -12,6 +12,19 @@
reg = <0x0>;
index = <0x0>;
include(p9-pib.dts.m4)dnl
+
+ i2cm@a1000 {
+ reg = <0x0 0xa1000 0x400>;
+ compatible = "ibm,power9-i2cm";
+ };
+ i2cm@a2000 {
+ reg = <0x0 0xa2000 0x400>;
+ compatible = "ibm,power9-i2cm";
+ };
+ i2cm@a3000 {
+ reg = <0x0 0xa3000 0x400>;
+ compatible = "ibm,power9-i2cm";
+ };
};
pib@8 {
@@ -21,5 +34,20 @@
reg = <0x8>;
index = <0x8>;
include(p9-pib.dts.m4)dnl
+
+ i2cm@a1000 {
+ reg = <0x0 0xa1000 0x400>;
+ compatible = "ibm,power9-i2cm";
+ };
+ i2cm@a2000 {
+ reg = <0x0 0xa2000 0x400>;
+ compatible = "ibm,power9-i2cm";
+ };
+ i2cm@a3000 {
+ reg = <0x0 0xa3000 0x400>;
+ compatible = "ibm,power9-i2cm";
+ };
+
+
};
};
Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> --- libpdbg/i2cm.c | 138 +++++++++++++++++++++++++++++++++++++++++++++++-- libpdbg/i2cm.h | 8 ++- p9-host.dts.m4 | 28 ++++++++++ 3 files changed, 169 insertions(+), 5 deletions(-)