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[OpenWrt-Devel,2/4] ath79: fix QCA9557 eth PLL settings

Message ID 20180806142104.17392-2-mail@david-bauer.net
State Accepted
Delegated to: John Crispin
Headers show
Series [OpenWrt-Devel,1/4] uboot-envtools: add ath79 target | expand

Commit Message

David Bauer Aug. 6, 2018, 2:21 p.m. UTC 
The QCA9557 dtsi is currently missing pll-handle and pll-regs for both
eth0 and eth1, therefore PLL settings won't be applied. This commit
fixes this behavior.

Signed-off-by: David Bauer <mail@david-bauer.net>
---
 target/linux/ath79/dts/qca9557.dtsi | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi
index 4f797a5543..e586f46433 100644
--- a/target/linux/ath79/dts/qca9557.dtsi
+++ b/target/linux/ath79/dts/qca9557.dtsi
@@ -109,7 +109,7 @@ 
 
 			pll: pll-controller@18050000 {
 				compatible = "qca,ar9557-pll",
-						"qca,qca9550-pll";
+						"qca,qca9550-pll", "syscon";
 				reg = <0x18050000 0x50>;
 
 				#clock-cells = <1>;
@@ -295,6 +295,9 @@ 
 &eth0 {
 	compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
 
+	pll-reg = <0 0x28 0>;
+	pll-handle = <&pll>;
+
 	pll-data = <0x82000101 0x80000101 0x80001313>;
 	phy-mode = "rgmii";
 
@@ -310,6 +313,9 @@ 
 &eth1 {
 	compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
 
+	pll-reg = <0 0x48 0>;
+	pll-handle = <&pll>;
+
 	pll-data = <0x82000101 0x80000101 0x80001313>;
 	phy-mode = "sgmii";