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[68.189.91.139]) by smtp.gmail.com with ESMTPSA id s207sm25344564pfs.60.2015.12.21.14.26.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Dec 2015 14:26:31 -0800 (PST) From: Pushpal Sidhu To: Date: Mon, 21 Dec 2015 14:25:13 -0800 Message-Id: <1450736720-8908-4-git-send-email-psidhu@gateworks.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1450736720-8908-1-git-send-email-psidhu@gateworks.com> References: <1450736720-8908-1-git-send-email-psidhu@gateworks.com> Cc: Luka Perkov Subject: [OpenWrt-Devel] [PATCH 03/10] imx6: ventana: add ecspi3 host controller for GW52xx X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Certain board revisions of the GW52xx support an SPI host controller with a single chip-select going to an off board connector. Signed-off-by: Tim Harvey Signed-off-by: Pushpal Sidhu --- ...ts-imx-ventana-add-spi-support-for-gw52xx.patch | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch diff --git a/target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch b/target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch new file mode 100644 index 0000000..a0fb48e --- /dev/null +++ b/target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch @@ -0,0 +1,35 @@ +Index: linux-4.3/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +=================================================================== +--- linux-4.3.orig/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi 2015-12-18 10:39:44.899158318 -0800 ++++ linux-4.3/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi 2015-12-18 10:43:27.000000000 -0800 +@@ -158,6 +158,14 @@ + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + }; + ++&ecspi3 { ++ fsl,spi-num-chipselects = <1>; ++ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi3>; ++ status = "okay"; ++}; ++ + &fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; +@@ -357,6 +365,15 @@ + >; + }; + ++ pinctrl_ecspi3: escpi3grp { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 ++ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 ++ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 ++ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 ++ >; ++ }; ++ + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0