| Message ID | 1429111522-12141-1-git-send-email-sven@open-mesh.com |
|---|---|
| State | Accepted |
| Headers | show |
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c index 272e410..298e80c 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c @@ -202,7 +202,7 @@ static void __init om5p_an_setup(void) ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_data.phy_mask = BIT(7); - ath79_eth0_pll_data.pll_1000 = 0x1a000000; + ath79_eth0_pll_data.pll_1000 = 0x02000000; ath79_eth0_pll_data.pll_100 = 0x00000101; ath79_eth0_pll_data.pll_10 = 0x00001313; ath79_register_eth(0);
The tx/rx delay bits in the ETH_XMII_CONTROL register have to be unset when the enable_rgmii_rx_delay/enable_rgmii_tx_delay will be set in the AT803x PHY. Othwise the throughput in gigabit mode is heavily reduced. Signed-off-by: Sven Eckelmann <sven@open-mesh.org> --- target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)