From patchwork Fri Feb 12 17:17:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Van Haaren, Harry" X-Patchwork-Id: 1439957 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=openvswitch.org (client-ip=140.211.166.138; helo=whitealder.osuosl.org; envelope-from=ovs-dev-bounces@openvswitch.org; receiver=) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DcgH408gzz9sVR for ; Sat, 13 Feb 2021 04:19:57 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 093088692C; Fri, 12 Feb 2021 17:19:56 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RBUdOrMzmG1Q; Fri, 12 Feb 2021 17:19:53 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by whitealder.osuosl.org (Postfix) with ESMTP id 5D0F086D6E; Fri, 12 Feb 2021 17:18:59 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 29146C1DA0; Fri, 12 Feb 2021 17:18:59 +0000 (UTC) X-Original-To: ovs-dev@openvswitch.org Delivered-To: ovs-dev@lists.linuxfoundation.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists.linuxfoundation.org (Postfix) with ESMTP id C16FAC1834 for ; Fri, 12 Feb 2021 17:18:56 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id A83DC6F945 for ; Fri, 12 Feb 2021 17:18:56 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DiNeMmr4b-zi for ; Fri, 12 Feb 2021 17:18:55 +0000 (UTC) Received: by smtp3.osuosl.org (Postfix, from userid 1001) id CBF3E6F937; Fri, 12 Feb 2021 17:18:47 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.8.0 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by smtp3.osuosl.org (Postfix) with ESMTPS id 93A3C6F8A0 for ; Fri, 12 Feb 2021 17:17:51 +0000 (UTC) IronPort-SDR: Hgv4L1ILsh2GYBxU5JChDoFviavayXmI7N6furJ65x5HVGswHbnjUQMNJGHI2VkxpXMU/Vhlll E+5Ysn47ZTYA== X-IronPort-AV: E=McAfee;i="6000,8403,9893"; a="201595235" X-IronPort-AV: E=Sophos;i="5.81,174,1610438400"; d="scan'208";a="201595235" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2021 09:17:51 -0800 IronPort-SDR: n4ez006+zETGH65Klh+4qRuqgA64JFIj1NA2iKDC6yUZo6z5akS+V5IquDvjC4Q44lHhryRsNZ 4dOJlt+GWBjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,174,1610438400"; d="scan'208";a="360485148" Received: from silpixa00400633.ir.intel.com ([10.237.213.44]) by orsmga003.jf.intel.com with ESMTP; 12 Feb 2021 09:17:49 -0800 From: Harry van Haaren To: ovs-dev@openvswitch.org Date: Fri, 12 Feb 2021 17:17:14 +0000 Message-Id: <20210212171718.2189798-13-harry.van.haaren@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210212171718.2189798-1-harry.van.haaren@intel.com> References: <20210104163653.2218575-1-harry.van.haaren@intel.com> <20210212171718.2189798-1-harry.van.haaren@intel.com> MIME-Version: 1.0 Cc: i.maximets@ovn.org Subject: [ovs-dev] [PATCH v9 12/16] dpdk: Cache result of CPU ISA checks. X-BeenThere: ovs-dev@openvswitch.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: ovs-dev-bounces@openvswitch.org Sender: "dev" As a small optimization, this patch caches the result of a CPU ISA check from DPDK. Particularly in the case of running the DPCLS autovalidator (which repeatedly probes subtables) this reduces the amount of CPU ISA lookups from the DPDK level. By caching them at the OVS/dpdk.c level, the ISA checks remain runtime for the CPU where they are executed, but subsequent checks for the same ISA feature become much cheaper. Signed-off-by: Harry van Haaren Co-authored-by: Cian Ferriter Signed-off-by: Cian Ferriter --- v8: Add NEWS entry. --- NEWS | 1 + lib/dpdk.c | 28 ++++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/NEWS b/NEWS index a5bb16da2..0a093e582 100644 --- a/NEWS +++ b/NEWS @@ -33,6 +33,7 @@ v2.15.0 - xx xxx xxxx - DPDK: * Removed support for vhost-user dequeue zero-copy. * Add support for DPDK 20.11. + * Cache results for CPU ISA checks, reduces overhead on repeated lookups. - Userspace datapath: * Add the 'pmd' option to "ovs-appctl dpctl/dump-flows", which restricts a flow dump to a single PMD thread if set. diff --git a/lib/dpdk.c b/lib/dpdk.c index 319540394..c883a4b8b 100644 --- a/lib/dpdk.c +++ b/lib/dpdk.c @@ -614,13 +614,33 @@ print_dpdk_version(void) puts(rte_version()); } +/* Avoid calling rte_cpu_get_flag_enabled() excessively, by caching the + * result of the call for each CPU flag in a static variable. To avoid + * allocating large numbers of static variables, use a uint8 as a bitfield. + * Note the macro must only return if the ISA check is done and available. + */ +#define ISA_CHECK_DONE_BIT (1 << 0) +#define ISA_AVAILABLE_BIT (1 << 1) + #define CHECK_CPU_FEATURE(feature, name_str, RTE_CPUFLAG) \ do { \ if (strncmp(feature, name_str, strlen(name_str)) == 0) { \ - int has_isa = rte_cpu_get_flag_enabled(RTE_CPUFLAG); \ - VLOG_DBG("CPU flag %s, available %s\n", name_str, \ - has_isa ? "yes" : "no"); \ - return true; \ + static uint8_t isa_check_##RTE_CPUFLAG; \ + int check = isa_check_##RTE_CPUFLAG & ISA_CHECK_DONE_BIT; \ + if (OVS_UNLIKELY(!check)) { \ + int has_isa = rte_cpu_get_flag_enabled(RTE_CPUFLAG); \ + VLOG_DBG("CPU flag %s, available %s\n", \ + name_str, has_isa ? "yes" : "no"); \ + isa_check_##RTE_CPUFLAG = ISA_CHECK_DONE_BIT; \ + if (has_isa) { \ + isa_check_##RTE_CPUFLAG |= ISA_AVAILABLE_BIT; \ + } \ + } \ + if (isa_check_##RTE_CPUFLAG & ISA_AVAILABLE_BIT) { \ + return true; \ + } else { \ + return false; \ + } \ } \ } while (0)