diff mbox series

pinctrl: aspeed: add pass-through pins and siopbi/siopbo

Message ID 20240120232813.32474-1-fr0st61te@gmail.com
State New
Headers show
Series pinctrl: aspeed: add pass-through pins and siopbi/siopbo | expand

Commit Message

Ivan Mikhaylov Jan. 20, 2024, 11:28 p.m. UTC 
Add THRU0-3 and SIOPBI/SIOPBO pin groups/functions.

Signed-off-by: Ivan Mikhaylov <fr0st61te@gmail.com>
---
 arch/arm/dts/ast2600.dtsi                | 20 ++++++++++++++++
 drivers/pinctrl/aspeed/pinctrl_ast2600.c | 30 ++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

Comments

Tom Rini March 4, 2024, 3:26 p.m. UTC | #1 
On Sun, Jan 21, 2024 at 02:28:13AM +0300, Ivan Mikhaylov wrote:

> Add THRU0-3 and SIOPBI/SIOPBO pin groups/functions.
> 
> Signed-off-by: Ivan Mikhaylov <fr0st61te@gmail.com>

Applied to u-boot/next, thanks!
diff mbox series

Patch

diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index beabcf14f8..43db80edfe 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -2028,6 +2028,26 @@ 
 		groups = "SPI2MOSI";
 	};
 
+	pinctrl_thru0_default: thru0_default {
+		function = "THRU0";
+		groups = "THRU0";
+	};
+
+	pinctrl_thru1_default: thru1_default {
+		function = "THRU1";
+		groups = "THRU1";
+	};
+
+	pinctrl_thru2_default: thru2_default {
+		function = "THRU2";
+		groups = "THRU2";
+	};
+
+	pinctrl_thru3_default: thru3_default {
+		function = "THRU3";
+		groups = "THRU3";
+	};
+
 	pinctrl_timer3_default: timer3_default {
 		function = "TIMER3";
 		groups = "TIMER3";
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
index 97e8b4ec9b..8a4f9705ca 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
@@ -267,6 +267,14 @@  static struct aspeed_sig_desc fmcquad_link[] = {
 	{ 0x438, GENMASK(5, 4), 0 },
 };
 
+static struct aspeed_sig_desc siopbi_link[] = {
+	{ 0x418, BIT(6), 0 },
+};
+
+static struct aspeed_sig_desc siopbo_link[] = {
+	{ 0x418, BIT(5), 0 },
+};
+
 static struct aspeed_sig_desc spi1_link[] = {
 	{ 0x438, GENMASK(13, 11), 0 },
 };
@@ -303,6 +311,22 @@  static struct aspeed_sig_desc spi2quad_link[] = {
 	{ 0x434, GENMASK(31, 30), 0 },
 };
 
+static struct aspeed_sig_desc thru0_link[] = {
+	{ 0x4bc, GENMASK(25, 24), 0 },
+};
+
+static struct aspeed_sig_desc thru1_link[] = {
+	{ 0x4bc, GENMASK(27, 26), 0 },
+};
+
+static struct aspeed_sig_desc thru2_link[] = {
+	{ 0x4bc, GENMASK(29, 28), 0 },
+};
+
+static struct aspeed_sig_desc thru3_link[] = {
+	{ 0x4bc, GENMASK(31, 30), 0 },
+};
+
 static struct aspeed_sig_desc fsi1[] = {
 	{ 0xd48, GENMASK(21, 20), 0 },
 };
@@ -458,6 +482,8 @@  static const struct aspeed_group_config ast2600_groups[] = {
 	{ "EMMC", ARRAY_SIZE(emmc_link), emmc_link },
 	{ "EMMCG8", ARRAY_SIZE(emmcg8_link), emmcg8_link },
 	{ "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link },
+	{ "SIOPBI", ARRAY_SIZE(siopbi_link), siopbi_link },
+	{ "SIOPBO", ARRAY_SIZE(siopbo_link), siopbo_link },
 	{ "SPI1", ARRAY_SIZE(spi1_link), spi1_link },
 	{ "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link },
 	{ "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link },
@@ -467,6 +493,10 @@  static const struct aspeed_group_config ast2600_groups[] = {
 	{ "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link },
 	{ "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link },
 	{ "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link },
+	{ "THRU0", ARRAY_SIZE(thru0_link), thru0_link },
+	{ "THRU1", ARRAY_SIZE(thru1_link), thru1_link },
+	{ "THRU2", ARRAY_SIZE(thru2_link), thru2_link },
+	{ "THRU3", ARRAY_SIZE(thru3_link), thru3_link },
 	{ "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link },
 	{ "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link },
 	{ "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link },