diff mbox series

[v4,02/13] dt-bindings: Add bindings for peci-aspeed

Message ID 20211123140706.2945700-3-iwona.winiarska@intel.com
State New
Headers show
Series Introduce PECI subsystem | expand

Commit Message

Winiarska, Iwona Nov. 23, 2021, 2:06 p.m. UTC 
Add device tree bindings for the peci-aspeed controller driver.

Co-developed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/peci/peci-aspeed.yaml | 109 ++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/peci/peci-aspeed.yaml

Comments

Billy Tsai Dec. 1, 2021, 10:38 a.m. UTC | #1 
Hi,

On 2021/11/23, 10:10 PM, "openbmc on behalf of Iwona Winiarska" <openbmc-bounces+billy_tsai=aspeedtech.com@lists.ozlabs.org on behalf of iwona.winiarska@intel.com> wrote:

    Add device tree bindings for the peci-aspeed controller driver.

    >   +  aspeed,clock-divider:
    >   +    description:
    >   +      This value determines PECI controller internal clock dividing
    >   +      rate. The divider will be calculated as 2 raised to the power of
    >   +      the given value.
    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   +    minimum: 0
    >   +    maximum: 7
    >   +    default: 0
    >   +
    >   +  aspeed,msg-timing:
    >   +    description:
    >   +      Message timing negotiation period. This value will determine the period
    >   +      of message timing negotiation to be issued by PECI controller. The unit
    >   +      of the programmed value is four times of PECI clock period.
    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   +    minimum: 0
    >   +    maximum: 255
    >   +    default: 1
    >   +
    >   +  aspeed,addr-timing:
    >   +    description:
    >   +      Address timing negotiation period. This value will determine the period
    >   +      of address timing negotiation to be issued by PECI controller. The unit
    >   +      of the programmed value is four times of PECI clock period.
    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   +    minimum: 0
    >   +    maximum: 255
    >   +    default: 1
I suggest deleting these three properties and replacing them with the following

aspeed,peci-bit-time:
        description:
          The bit time driven by PECI controller. The unit of the value is Hz.
    minimum: 2000
    maximum: 1000000

And the driver should use this property to caculate the appropriate clock-divider,
msg-timing and addr-timing, instead of exposing hardware registers to dts.

    >    [...]
    >   +examples:
    >   +  - |
    >   +    #include <dt-bindings/interrupt-controller/arm-gic.h>
    >   +    #include <dt-bindings/clock/ast2600-clock.h>
    >   +    peci-controller@1e78b000 {
    >   +      compatible = "aspeed,ast2600-peci";
    >   +      reg = <0x1e78b000 0x100>;
    >   +      interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    >   +      clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
    >   +      resets = <&syscon ASPEED_RESET_PECI>;
    >   +      cmd-timeout-ms = <1000>;
    >   +      aspeed,clock-divider = <0>;
    >   +      aspeed,msg-timing = <1>;
    >   +      aspeed,addr-timing = <1>;
    >   +      aspeed,rd-sampling-point = <8>;
    >   +    };
    >   +...
    -- 
    2.31.1

Thanks

Best Regards,
Billy Tsai
Zev Weiss Dec. 2, 2021, 1:54 a.m. UTC | #2 
On Wed, Dec 01, 2021 at 02:38:04AM PST, Billy Tsai wrote:
>Hi,
>
>On 2021/11/23, 10:10 PM, "openbmc on behalf of Iwona Winiarska" <openbmc-bounces+billy_tsai=aspeedtech.com@lists.ozlabs.org on behalf of iwona.winiarska@intel.com> wrote:
>
>    Add device tree bindings for the peci-aspeed controller driver.
>
>    >   +  aspeed,clock-divider:
>    >   +    description:
>    >   +      This value determines PECI controller internal clock dividing
>    >   +      rate. The divider will be calculated as 2 raised to the power of
>    >   +      the given value.
>    >   +    $ref: /schemas/types.yaml#/definitions/uint32
>    >   +    minimum: 0
>    >   +    maximum: 7
>    >   +    default: 0
>    >   +
>    >   +  aspeed,msg-timing:
>    >   +    description:
>    >   +      Message timing negotiation period. This value will determine the period
>    >   +      of message timing negotiation to be issued by PECI controller. The unit
>    >   +      of the programmed value is four times of PECI clock period.
>    >   +    $ref: /schemas/types.yaml#/definitions/uint32
>    >   +    minimum: 0
>    >   +    maximum: 255
>    >   +    default: 1
>    >   +
>    >   +  aspeed,addr-timing:
>    >   +    description:
>    >   +      Address timing negotiation period. This value will determine the period
>    >   +      of address timing negotiation to be issued by PECI controller. The unit
>    >   +      of the programmed value is four times of PECI clock period.
>    >   +    $ref: /schemas/types.yaml#/definitions/uint32
>    >   +    minimum: 0
>    >   +    maximum: 255
>    >   +    default: 1
>I suggest deleting these three properties and replacing them with the following
>
>aspeed,peci-bit-time:
>        description:
>          The bit time driven by PECI controller. The unit of the value is Hz.
>    minimum: 2000
>    maximum: 1000000
>
>And the driver should use this property to caculate the appropriate clock-divider,
>msg-timing and addr-timing, instead of exposing hardware registers to dts.
>

Or perhaps just 'bus-frequency' a la i2c-aspeed, gpio-aspeed-sgpio, etc?


Zev
Billy Tsai Dec. 2, 2021, 2:31 a.m. UTC | #3 
Hi Zev,

On 2021/12/2, 9:55 AM, "Zev Weiss" <zweiss@equinix.com> wrote:

    On Wed, Dec 01, 2021 at 02:38:04AM PST, Billy Tsai wrote:
    >   >Hi,
    >   >
    >   >On 2021/11/23, 10:10 PM, "openbmc on behalf of Iwona Winiarska" <openbmc-bounces+billy_tsai=aspeedtech.com@lists.ozlabs.org on behalf of iwona.winiarska@intel.com> wrote:
    >   >
    >   >    Add device tree bindings for the peci-aspeed controller driver.
    >   >
    >   >    >   +  aspeed,clock-divider:
    >   >    >   +    description:
    >   >    >   +      This value determines PECI controller internal clock dividing
    >   >    >   +      rate. The divider will be calculated as 2 raised to the power of
    >   >    >   +      the given value.
    >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   >    >   +    minimum: 0
    >   >    >   +    maximum: 7
    >   >    >   +    default: 0
    >   >    >   +
    >   >    >   +  aspeed,msg-timing:
    >   >    >   +    description:
    >   >    >   +      Message timing negotiation period. This value will determine the period
    >   >    >   +      of message timing negotiation to be issued by PECI controller. The unit
    >   >    >   +      of the programmed value is four times of PECI clock period.
    >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   >    >   +    minimum: 0
    >   >    >   +    maximum: 255
    >   >    >   +    default: 1
    >   >    >   +
    >   >    >   +  aspeed,addr-timing:
    >   >    >   +    description:
    >   >    >   +      Address timing negotiation period. This value will determine the period
    >   >    >   +      of address timing negotiation to be issued by PECI controller. The unit
    >   >    >   +      of the programmed value is four times of PECI clock period.
    >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   >    >   +    minimum: 0
    >   >    >   +    maximum: 255
    >   >    >   +    default: 1
    >   >I suggest deleting these three properties and replacing them with the following
    >   >
    >   >aspeed,peci-bit-time:
    >   >        description:
    >   >          The bit time driven by PECI controller. The unit of the value is Hz.
    >   >    minimum: 2000
    >   >    maximum: 1000000
    >   >
    >   >And the driver should use this property to caculate the appropriate clock-divider,
    >   >msg-timing and addr-timing, instead of exposing hardware registers to dts.
    >   >

    >   Or perhaps just 'bus-frequency' a la i2c-aspeed, gpio-aspeed-sgpio, etc?

It's a good ideal for the consistency.

Thanks

Best Regards,
Billy Tsai
Winiarska, Iwona Dec. 7, 2021, 6:15 p.m. UTC | #4 
On Thu, 2021-12-02 at 02:31 +0000, Billy Tsai wrote:
> Hi Zev,
> 
> On 2021/12/2, 9:55 AM, "Zev Weiss" <zweiss@equinix.com> wrote:
> 
>     On Wed, Dec 01, 2021 at 02:38:04AM PST, Billy Tsai wrote:
>     >   >Hi,
>     >   >
>     >   >On 2021/11/23, 10:10 PM, "openbmc on behalf of Iwona Winiarska"
> <openbmc-bounces+billy_tsai=aspeedtech.com@lists.ozlabs.org on behalf of
> iwona.winiarska@intel.com> wrote:
>     >   >
>     >   >    Add device tree bindings for the peci-aspeed controller driver.
>     >   >
>     >   >    >   +  aspeed,clock-divider:
>     >   >    >   +    description:
>     >   >    >   +      This value determines PECI controller internal clock
> dividing
>     >   >    >   +      rate. The divider will be calculated as 2 raised to
> the power of
>     >   >    >   +      the given value.
>     >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
>     >   >    >   +    minimum: 0
>     >   >    >   +    maximum: 7
>     >   >    >   +    default: 0
>     >   >    >   +
>     >   >    >   +  aspeed,msg-timing:
>     >   >    >   +    description:
>     >   >    >   +      Message timing negotiation period. This value will
> determine the period
>     >   >    >   +      of message timing negotiation to be issued by PECI
> controller. The unit
>     >   >    >   +      of the programmed value is four times of PECI clock
> period.
>     >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
>     >   >    >   +    minimum: 0
>     >   >    >   +    maximum: 255
>     >   >    >   +    default: 1
>     >   >    >   +
>     >   >    >   +  aspeed,addr-timing:
>     >   >    >   +    description:
>     >   >    >   +      Address timing negotiation period. This value will
> determine the period
>     >   >    >   +      of address timing negotiation to be issued by PECI
> controller. The unit
>     >   >    >   +      of the programmed value is four times of PECI clock
> period.
>     >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
>     >   >    >   +    minimum: 0
>     >   >    >   +    maximum: 255
>     >   >    >   +    default: 1
>     >   >I suggest deleting these three properties and replacing them with the
> following
>     >   >
>     >   >aspeed,peci-bit-time:
>     >   >        description:
>     >   >          The bit time driven by PECI controller. The unit of the
> value is Hz.
>     >   >    minimum: 2000
>     >   >    maximum: 1000000
>     >   >
>     >   >And the driver should use this property to caculate the appropriate
> clock-divider,
>     >   >msg-timing and addr-timing, instead of exposing hardware registers to
> dts.
>     >   >
> 
>     >   Or perhaps just 'bus-frequency' a la i2c-aspeed, gpio-aspeed-sgpio,
> etc?
> 
> It's a good ideal for the consistency.

If we want to go with passing frequency - I would prefer to go with "clock-
frequency" and use clock framework for exposing it to peci-aspeed (as I
mentioned in reply to patch 05).

What do you think?

Thanks
-Iwona

> 
> Thanks
> 
> Best Regards,
> Billy Tsai
> 
>
Billy Tsai Dec. 8, 2021, 2:23 a.m. UTC | #5 
Hi Iwona,

On 2021/12/8, 2:30 AM, "Winiarska, Iwona" <iwona.winiarska@intel.com> wrote:

    On Thu, 2021-12-02 at 02:31 +0000, Billy Tsai wrote:
    >   > Hi Zev,
    >   > 
    >   > On 2021/12/2, 9:55 AM, "Zev Weiss" <zweiss@equinix.com> wrote:
    >   > 
    >   >     On Wed, Dec 01, 2021 at 02:38:04AM PST, Billy Tsai wrote:
    >   >     >   >Hi,
    >   >     >   >
    >   >     >   >On 2021/11/23, 10:10 PM, "openbmc on behalf of Iwona Winiarska"
    >   > <openbmc-bounces+billy_tsai=aspeedtech.com@lists.ozlabs.org on behalf of
    >   > iwona.winiarska@intel.com> wrote:
    >   >     >   >
    >   >     >   >    Add device tree bindings for the peci-aspeed controller driver.
    >   >     >   >
    >   >     >   >    >   +  aspeed,clock-divider:
    >   >     >   >    >   +    description:
    >   >     >   >    >   +      This value determines PECI controller internal clock
    >   > dividing
    >   >     >   >    >   +      rate. The divider will be calculated as 2 raised to
    >   > the power of
    >   >     >   >    >   +      the given value.
    >   >     >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   >     >   >    >   +    minimum: 0
    >   >     >   >    >   +    maximum: 7
    >   >     >   >    >   +    default: 0
    >   >     >   >    >   +
    >   >     >   >    >   +  aspeed,msg-timing:
    >   >     >   >    >   +    description:
    >   >     >   >    >   +      Message timing negotiation period. This value will
    >   > determine the period
    >   >     >   >    >   +      of message timing negotiation to be issued by PECI
    >   > controller. The unit
    >   >     >   >    >   +      of the programmed value is four times of PECI clock
    >   > period.
    >   >     >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   >     >   >    >   +    minimum: 0
    >   >     >   >    >   +    maximum: 255
    >   >     >   >    >   +    default: 1
    >   >     >   >    >   +
    >   >     >   >    >   +  aspeed,addr-timing:
    >   >     >   >    >   +    description:
    >   >     >   >    >   +      Address timing negotiation period. This value will
    >   > determine the period
    >   >     >   >    >   +      of address timing negotiation to be issued by PECI
    >   > controller. The unit
    >   >     >   >    >   +      of the programmed value is four times of PECI clock
    >   > period.
    >   >     >   >    >   +    $ref: /schemas/types.yaml#/definitions/uint32
    >   >     >   >    >   +    minimum: 0
    >   >     >   >    >   +    maximum: 255
    >   >     >   >    >   +    default: 1
    >   >     >   >I suggest deleting these three properties and replacing them with the
    >   > following
    >   >     >   >
    >   >     >   >aspeed,peci-bit-time:
    >   >     >   >        description:
    >   >     >   >          The bit time driven by PECI controller. The unit of the
    >   > value is Hz.
    >   >     >   >    minimum: 2000
    >   >     >   >    maximum: 1000000
    >   >     >   >
    >   >     >   >And the driver should use this property to caculate the appropriate
    >   > clock-divider,
    >   >     >   >msg-timing and addr-timing, instead of exposing hardware registers to
    >   > dts.
    >   >     >   >
    >   > 
    >   >     >   Or perhaps just 'bus-frequency' a la i2c-aspeed, gpio-aspeed-sgpio,
    >   > etc?
    >   > 
    >   > It's a good ideal for the consistency.

    >   If we want to go with passing frequency - I would prefer to go with "clock-
    >   frequency" and use clock framework for exposing it to peci-aspeed (as I
    >   mentioned in reply to patch 05).

    >   What do you think?

Good.
It looks that "clock-frequency" is more common usage.

Thanks

Best Regards,
Billy Tsai
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/peci/peci-aspeed.yaml b/Documentation/devicetree/bindings/peci/peci-aspeed.yaml
new file mode 100644
index 000000000000..2929d1e000d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/peci/peci-aspeed.yaml
@@ -0,0 +1,109 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/peci/peci-aspeed.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed PECI Bus Device Tree Bindings
+
+maintainers:
+  - Iwona Winiarska <iwona.winiarska@intel.com>
+  - Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
+
+allOf:
+  - $ref: peci-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2400-peci
+      - aspeed,ast2500-peci
+      - aspeed,ast2600-peci
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description:
+      Clock source for PECI controller. Should reference the external
+      oscillator clock.
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  cmd-timeout-ms:
+    minimum: 1
+    maximum: 1000
+    default: 1000
+
+  aspeed,clock-divider:
+    description:
+      This value determines PECI controller internal clock dividing
+      rate. The divider will be calculated as 2 raised to the power of
+      the given value.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 7
+    default: 0
+
+  aspeed,msg-timing:
+    description:
+      Message timing negotiation period. This value will determine the period
+      of message timing negotiation to be issued by PECI controller. The unit
+      of the programmed value is four times of PECI clock period.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 255
+    default: 1
+
+  aspeed,addr-timing:
+    description:
+      Address timing negotiation period. This value will determine the period
+      of address timing negotiation to be issued by PECI controller. The unit
+      of the programmed value is four times of PECI clock period.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 255
+    default: 1
+
+  aspeed,rd-sampling-point:
+    description:
+      Read sampling point selection. The whole period of a bit time will be
+      divided into 16 time frames. This value will determine the time frame
+      in which the controller will sample PECI signal for data read back.
+      Usually in the middle of a bit time is the best.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 15
+    default: 8
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/ast2600-clock.h>
+    peci-controller@1e78b000 {
+      compatible = "aspeed,ast2600-peci";
+      reg = <0x1e78b000 0x100>;
+      interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
+      resets = <&syscon ASPEED_RESET_PECI>;
+      cmd-timeout-ms = <1000>;
+      aspeed,clock-divider = <0>;
+      aspeed,msg-timing = <1>;
+      aspeed,addr-timing = <1>;
+      aspeed,rd-sampling-point = <8>;
+    };
+...