| Message ID | 20210922103116.30652-7-chin-ting_kuo@aspeedtech.com |
|---|---|
| State | New |
| Headers | show |
| Series | ASPEED SD/eMMC controller clock configuration | expand |
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 1b47be1704f8..d083de1d6567 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -597,7 +597,7 @@ status = "disabled"; emmc: sdhci@1e750100 { - compatible = "aspeed,ast2600-sdhci"; + compatible = "aspeed,ast2600-emmc"; reg = <0x100 0x100>; sdhci,auto-cmd12; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
Since the eMMC device's delay parameters are different from the SD's, a new compatible should be used to distinguish between eMMC and SD device. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> --- arch/arm/boot/dts/aspeed-g6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)