From patchwork Thu Sep 2 02:18:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 1523458 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H0Pmr6GyKz9sPf for ; Thu, 2 Sep 2021 12:21:16 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4H0Pmr5ZMHz2ymS for ; Thu, 2 Sep 2021 12:21:16 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chiawei_wang@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4H0Plp0QLpz2xrx; Thu, 2 Sep 2021 12:20:21 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 1821xBgw068911; Thu, 2 Sep 2021 09:59:11 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Sep 2021 10:18:15 +0800 From: Chia-Wei Wang To: , , , , , , , , , Subject: [PATCH v2 3/3] ARM: dts: aspeed: Add uart routing to device tree Date: Thu, 2 Sep 2021 10:18:17 +0800 Message-ID: <20210902021817.17506-5-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210902021817.17506-1-chiawei_wang@aspeedtech.com> References: <20210902021817.17506-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 1821xBgw068911 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Add LPC uart routing to the device tree for Aspeed AST25xx/AST26xx SoCs. Signed-off-by: Chia-Wei Wang --- arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++ arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 329eaeef66fb..d3da5c948165 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -492,6 +492,12 @@ #reset-cells = <1>; }; + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2500-uart-routing"; + reg = <0x98 0x8>; + status = "disabled"; + }; + lhc: lhc@a0 { compatible = "aspeed,ast2500-lhc"; reg = <0xa0 0x24 0xc8 0x8>; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index f96607b7b4e2..c287d9dba118 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -523,6 +523,12 @@ #reset-cells = <1>; }; + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + status = "disabled"; + }; + ibt: ibt@140 { compatible = "aspeed,ast2600-ibt-bmc"; reg = <0x140 0x18>;