| Message ID | 20200911034631.8473-5-chiawei_wang@aspeedtech.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Remove LPC register partitioning | expand |
On Fri, Sep 11, 2020 at 5:47 AM Chia-Wei, Wang <chiawei_wang@aspeedtech.com> wrote: > The LPC register offsets are fixed to adapt to the LPC DTS change, > where the LPC partitioning is removed. > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> I can apply this one patch if I get a review from one of the Aspeed pinctrl maintainer. Andrew? Yours, Linus Walleij
On Tue, 29 Sep 2020, at 22:12, Linus Walleij wrote: > On Fri, Sep 11, 2020 at 5:47 AM Chia-Wei, Wang > <chiawei_wang@aspeedtech.com> wrote: > > > The LPC register offsets are fixed to adapt to the LPC DTS change, > > where the LPC partitioning is removed. > > > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> > > I can apply this one patch if I get a review from one of the > Aspeed pinctrl maintainer. > > Andrew? There needs to be a v2 of the series that fixes the binding documentation, which will drive some discussion about backwards compatibility. So lets not apply this patch just yet. Thanks for touching base! Andrew
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 0cab4c2576e2..98e62333fa54 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -60,7 +60,7 @@ #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } /* LHCR0 is offset from the end of the H8S/2168-compatible registers */ -#define LHCR0 0x20 +#define LHCR0 0xa0 #define GFX064 0x64 #define B14 0
The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)