| Message ID | 20190412140132.39764-1-fran.hsu@quantatw.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [dev-5.0,v2,1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC machine | expand |
Sorry for the delay on this. On Fri, Apr 12, 2019 at 7:01 AM <fran.hsu@quantatw.com> wrote: > > From: FranHsu <Fran.Hsu@quantatw.com> > > Add a common device tree include file for NPCM730. > > Signed-off-by: FranHsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> > --- > arch/arm/boot/dts/nuvoton-npcm730.dtsi | 57 ++++++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi > > diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > new file mode 100644 > index 000000000000..20e13489b993 > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > @@ -0,0 +1,57 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com > +// Copyright 2018 Google, Inc. > + > +#include "nuvoton-common-npcm7xx.dtsi" > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm750-smp"; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + soc { > + timer@3fe600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x3fe600 0x20>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_HIGH)>; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + }; > + }; > + > + ahb { > + udc9:udc@f0839000 { > + compatible = "nuvoton,npcm750-udc"; > + reg = <0xf0839000 0x1000 > + 0xfffd0000 0x800>; > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + clocks = <&clk NPCM7XX_CLK_SU>; > + clock-names = "clk_usb_bridge"; > + }; > + }; > +}; > -- > 2.21.0 >
diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..20e13489b993 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; + + ahb { + udc9:udc@f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd0000 0x800>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + }; +};