| Message ID | 20180209051158.32354-4-joel@jms.id.au |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | LPC fixes | expand |
On Fri, 2018-02-09 at 15:41 +1030, Joel Stanley wrote: > The LPC Host Interface Controller is part of a BMC SoC that is used for > communication with the host. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > .../devicetree/bindings/mfd/aspeed-lpc.txt | 39 ++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > index 514d82ced95b..c40b707df907 100644 > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > @@ -109,6 +109,45 @@ lpc: lpc@1e789000 { > }; > }; > > +BMC Node Children > +================== > + > +LPC Host Interface Controller > +------------------- > + > +The LPC Host Interface Controller manages functions exposed to the host such as > +LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART > +management and bus snoop configuration. > + > +Required properties: > + > +- compatible: One of: > + "aspeed,ast2400-lpc-ctrl"; > + "aspeed,ast2500-lpc-ctrl"; > + > +- reg: contains offset/length values of the LHC memory regions It's annoying to reconcile this with the datasheet. I think LHC should be HIC here: The LHC registers concern themselves with configuration of the LPC bus itself, whilst the HIC registers control the behaviour of the BMC with respect to requests over the LPC bus. This driver is for the HIC part of the IP, so we should try to keep the documentation consistent. Cheers, Andrew > + > +- clocks: contains a phandle to the syscon node describing the clocks. > + There should then be one cell representing the clock to use > + > +- memory-region: A phandle to a reserved_memory region to be used for the LPC > + to AHB mapping > + > +- flash: A phandle to the SPI flash controller containing the flash to > + be exposed over the LPC to AHB mapping > + > +Example: > + > +lpc-host@80 { > + lpc_ctrl: lpc-ctrl@0 { > + compatible = "aspeed,ast2500-lpc-ctrl"; > + reg = <0x0 0x80>; > + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; > + memory-region = <&flash_memory>; > + flash = <&spi>; > + }; > +}; > + > Host Node Children > ================== >
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..c40b707df907 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -109,6 +109,45 @@ lpc: lpc@1e789000 { }; }; +BMC Node Children +================== + +LPC Host Interface Controller +------------------- + +The LPC Host Interface Controller manages functions exposed to the host such as +LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART +management and bus snoop configuration. + +Required properties: + +- compatible: One of: + "aspeed,ast2400-lpc-ctrl"; + "aspeed,ast2500-lpc-ctrl"; + +- reg: contains offset/length values of the LHC memory regions + +- clocks: contains a phandle to the syscon node describing the clocks. + There should then be one cell representing the clock to use + +- memory-region: A phandle to a reserved_memory region to be used for the LPC + to AHB mapping + +- flash: A phandle to the SPI flash controller containing the flash to + be exposed over the LPC to AHB mapping + +Example: + +lpc-host@80 { + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; +}; + Host Node Children ==================
The LPC Host Interface Controller is part of a BMC SoC that is used for communication with the host. Signed-off-by: Joel Stanley <joel@jms.id.au> --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+)