diff mbox series

[u-boot,v2016.07-aspeed-openbmc] aspeed/flash: Add MX66L1G45G chip

Message ID 1559156179-60850-1-git-send-email-anoo@linux.ibm.com
State Accepted, archived
Headers show
Series [u-boot,v2016.07-aspeed-openbmc] aspeed/flash: Add MX66L1G45G chip | expand

Commit Message

Adriana Kobylak May 29, 2019, 6:56 p.m. UTC
From: Adriana Kobylak <anoo@us.ibm.com>

The MX66L1G45G is a 128MB SPI NOR flash chip to be used in
Swift machines which are AST2500 systems.

Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
---
 arch/arm/mach-aspeed/flash.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Cédric Le Goater June 3, 2019, 5:59 a.m. UTC | #1
On 29/05/2019 20:56, Adriana Kobylak wrote:
> From: Adriana Kobylak <anoo@us.ibm.com>
> 
> The MX66L1G45G is a 128MB SPI NOR flash chip to be used in
> Swift machines which are AST2500 systems.

It looks correct to me.



Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.

> 
> Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
> ---
>  arch/arm/mach-aspeed/flash.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c
> index db69d51..cc59707 100644
> --- a/arch/arm/mach-aspeed/flash.c
> +++ b/arch/arm/mach-aspeed/flash.c
> @@ -78,6 +78,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];		/* FLASH chips info */
>  #define MX25L12805D		0x1820C2
>  #define MX25L25635E		0x1920C2
>  #define MX66L51235F		0x1A20C2
> +#define MX66L1G45G		0x1B20C2
>  #define SST25VF016B		0x4125bf
>  #define SST25VF064C		0x4b25bf
>  #define SST25VF040B		0x8d25bf
> @@ -1077,6 +1078,20 @@ static ulong flash_get_size (ulong base, flash_info_t *info)
>  			ReadClk  = 50;
>  			break;
>  
> +		case MX66L1G45G:
> +			info->sector_count = 2048;
> +			info->size = 0x8000000;
> +			erase_region_size  = 0x10000;
> +			info->readcmd = 0x0b;
> +			info->dualport = 0;
> +			info->dummybyte = 1;
> +			info->buffersize = 256;
> +			WriteClk = 50;
> +			EraseClk = 25;
> +			ReadClk  = 50;
> +			info->address32 = 1;
> +			break;
> +
>  		case SST25VF016B:
>  			info->sector_count = 32;
>  			info->size = 0x200000;
>
Joel Stanley June 3, 2019, 9 a.m. UTC | #2
On Mon, 3 Jun 2019 at 05:59, Cédric Le Goater <clg@kaod.org> wrote:
>
> On 29/05/2019 20:56, Adriana Kobylak wrote:
> > From: Adriana Kobylak <anoo@us.ibm.com>
> >
> > The MX66L1G45G is a 128MB SPI NOR flash chip to be used in
> > Swift machines which are AST2500 systems.
>
> It looks correct to me.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks.

Merged into v2016.07-aspeed-openbmc.
diff mbox series

Patch

diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c
index db69d51..cc59707 100644
--- a/arch/arm/mach-aspeed/flash.c
+++ b/arch/arm/mach-aspeed/flash.c
@@ -78,6 +78,7 @@  flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];		/* FLASH chips info */
 #define MX25L12805D		0x1820C2
 #define MX25L25635E		0x1920C2
 #define MX66L51235F		0x1A20C2
+#define MX66L1G45G		0x1B20C2
 #define SST25VF016B		0x4125bf
 #define SST25VF064C		0x4b25bf
 #define SST25VF040B		0x8d25bf
@@ -1077,6 +1078,20 @@  static ulong flash_get_size (ulong base, flash_info_t *info)
 			ReadClk  = 50;
 			break;
 
+		case MX66L1G45G:
+			info->sector_count = 2048;
+			info->size = 0x8000000;
+			erase_region_size  = 0x10000;
+			info->readcmd = 0x0b;
+			info->dualport = 0;
+			info->dummybyte = 1;
+			info->buffersize = 256;
+			WriteClk = 50;
+			EraseClk = 25;
+			ReadClk  = 50;
+			info->address32 = 1;
+			break;
+
 		case SST25VF016B:
 			info->sector_count = 32;
 			info->size = 0x200000;