From patchwork Thu Oct 27 23:40:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaghathiswari Rankappagounder Natarajan X-Patchwork-Id: 687984 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t4k1Y6Mdpz9sD5 for ; Fri, 28 Oct 2016 10:41:37 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=dKVrTSsT; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3t4k1Y5K59zDvRW for ; Fri, 28 Oct 2016 10:41:37 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; 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Thu, 27 Oct 2016 16:40:53 -0700 (PDT) Received: from jaghu22.svl.corp.google.com ([100.123.242.38]) by smtp.gmail.com with ESMTPSA id y189sm14147467pfy.34.2016.10.27.16.40.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 27 Oct 2016 16:40:52 -0700 (PDT) From: Jaghathiswari Rankappagounder Natarajan To: joel@jms.id.au, openbmc@lists.ozlabs.org Subject: [PATCH linux v1 3/3] devicetree: Add support in Zaius for PWM controller and four PWM outputs(fans) Date: Thu, 27 Oct 2016 16:40:22 -0700 Message-Id: <1477611622-28120-4-git-send-email-jaghu@google.com> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1477611622-28120-1-git-send-email-jaghu@google.com> References: <1477611622-28120-1-git-send-email-jaghu@google.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jaghathiswari Rankappagounder Natarajan MIME-Version: 1.0 Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Signed-off-by: Jaghathiswari Rankappagounder Natarajan --- arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 63 ++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) -- 2.8.0.rc3.226.g39d4020 diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index eef045b..82a12dc 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -83,6 +83,69 @@ gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>; }; }; + + pwm_controller { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x78>; + compatible = "aspeed-pwm-controller"; + clock_enable = /bits/ 8 <0x01>; + clock_source = /bits/ 8 <0x00>; + typem_pwm_clock = <5 0 95>; + }; + + pwm0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x78>; + compatible = "aspeed-pwm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default>; + pwm_channel_enable = /bits/ 8 <0x00>; + pwm_type = /bits/ 8 <0x00>; + rising = /bits/ 8 <0x00>; + falling = /bits/ 8 <0x00>; + }; + + pwm1 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x78>; + compatible = "aspeed-pwm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_default>; + pwm_channel_enable = /bits/ 8 <0x01>; + pwm_type = /bits/ 8 <0x00>; + rising = /bits/ 8 <0x00>; + falling = /bits/ 8 <0x00>; + }; + + pwm2 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x78>; + compatible = "aspeed-pwm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2_default>; + pwm_channel_enable = /bits/ 8 <0x02>; + pwm_type = /bits/ 8 <0x00>; + rising = /bits/ 8 <0x00>; + falling = /bits/ 8 <0x00>; + }; + + pwm3 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x78>; + compatible = "aspeed-pwm-dev"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_default>; + pwm_channel_enable = /bits/ 8 <0x03>; + pwm_type = /bits/ 8 <0x00>; + rising = /bits/ 8 <0x00>; + falling = /bits/ 8 <0x00>; + }; + }; &uart5 {