| Message ID | 1476448684-6149-13-git-send-email-clg@kaod.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
On Fri, Oct 14, 2016 at 11:08 PM, Cédric Le Goater <clg@kaod.org> wrote: > Try to improve the speed of transfers when doing DMAs This could get squashed into the DMA adding patch I think. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> > --- > drivers/mtd/spi-nor/aspeed-smc.c | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-)
Hello Joel, On 10/17/2016 07:04 AM, Joel Stanley wrote: > On Fri, Oct 14, 2016 at 11:08 PM, Cédric Le Goater <clg@kaod.org> wrote: >> Try to improve the speed of transfers when doing DMAs > > This could get squashed into the DMA adding patch I think. If you haven't pushed yet, you can drop this one, it does not change anything in fact. I am currently looking at introducing some timing support to speed up reading on the SPI, like pflash does and I am shuffling the code quite a lot to isolate the different settings. Just to say they are more changes to come to cleanup the driver. Thanks for the review, C. > >> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> > > Reviewed-by: Joel Stanley <joel@jms.id.au> > >> --- >> drivers/mtd/spi-nor/aspeed-smc.c | 11 +++++++---- >> 1 file changed, 7 insertions(+), 4 deletions(-)
On Mon, Oct 17, 2016 at 5:12 PM, Cédric Le Goater <clg@kaod.org> wrote: > Hello Joel, > > On 10/17/2016 07:04 AM, Joel Stanley wrote: >> On Fri, Oct 14, 2016 at 11:08 PM, Cédric Le Goater <clg@kaod.org> wrote: >>> Try to improve the speed of transfers when doing DMAs >> >> This could get squashed into the DMA adding patch I think. > > If you haven't pushed yet, you can drop this one, it does not > change anything in fact. > > I am currently looking at introducing some timing support > to speed up reading on the SPI, like pflash does and I am > shuffling the code quite a lot to isolate the different settings. > > > Just to say they are more changes to come to cleanup the driver. Okay, great. I will hold off merging the patches for a little white. We will need to commit them some time this week though. If they are not the final version then that is okay. Once you have something ready for upstream, we should cc Ben H (who as you know wrote pflash) for his thoughts. We need to do that this week as he won't have much time next week. Cheers, Joel
On 10/17/2016 11:10 AM, Joel Stanley wrote: > On Mon, Oct 17, 2016 at 5:12 PM, Cédric Le Goater <clg@kaod.org> wrote: >> Hello Joel, >> >> On 10/17/2016 07:04 AM, Joel Stanley wrote: >>> On Fri, Oct 14, 2016 at 11:08 PM, Cédric Le Goater <clg@kaod.org> wrote: >>>> Try to improve the speed of transfers when doing DMAs >>> >>> This could get squashed into the DMA adding patch I think. >> >> If you haven't pushed yet, you can drop this one, it does not >> change anything in fact. >> >> I am currently looking at introducing some timing support >> to speed up reading on the SPI, like pflash does and I am >> shuffling the code quite a lot to isolate the different settings. >> >> >> Just to say they are more changes to come to cleanup the driver. > > Okay, great. > > I will hold off merging the patches for a little white. We will need > to commit them some time this week though. If they are not the final > version then that is okay. I am tired of the little fixes so I will make one big patch for the aspeed smc, AST2400 and AST2500, then a couple more for the dts, plus one for the dma (as I am not sure it is useful). I have another one pending for timing optimizations but that is too drafty for the moment. Hopefully, I can make the patchset common with mainline with a first revert of what we have today in openbmc and some API fixes for 4.8. > Once you have something ready for upstream, we should cc Ben H (who > as you know wrote pflash) for his thoughts. We need to do that this > week as he won't have much time next week. Sure. I have questions on the default settings. Some are strapped by hardware, like the Div 2, depending on the controller type, some are not but we would like that to work in all cases. I have started to maintain a static table per chip jedec for these in the driver. I am not sure of the approach, but first, let's get a clean common base to work with. Thanks, C.
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index ae2d9bc643c3..40e48372865a 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -211,6 +211,7 @@ enum smc_ctl_reg_value { smc_base, /* base value without mode for other commands */ smc_read, /* command reg for (maybe fast) reads */ smc_write, /* command reg for writes with timings */ + smc_fread, /* command reg for (maybe faster?) reads */ smc_num_ctl_reg_values /* last value to get count of commands */ }; @@ -347,9 +348,6 @@ static inline void aspeed_smc_chip_configure(struct aspeed_smc_per_chip *chip, writel(ctl, chip->ctl); } -/* - * TODO: configure FREAD mode - */ static int aspeed_smc_dma_start(struct aspeed_smc_per_chip *chip, u32 offset, void *buf, size_t length, int is_write) @@ -359,7 +357,7 @@ static int aspeed_smc_dma_start(struct aspeed_smc_per_chip *chip, int ret; aspeed_smc_chip_configure(chip, is_write ? chip->ctl_val[smc_write] : - chip->ctl_val[smc_base]); + chip->ctl_val[smc_fread]); dev_dbg(chip->nor.dev, "DMA %s to=0x%08x len=0x%08x\n", is_write ? "write" : "read", offset, length); @@ -823,6 +821,11 @@ static int aspeed_smc_probe(struct platform_device *pdev) if (err) continue; + chip->ctl_val[smc_fread] = chip->ctl_val[smc_base] | + /* Not sure this is that fast */ + spi_control_fill_opcode(SPINOR_OP_READ_FAST) | + CONTROL_SPI_COMMAND_MODE_FREAD; + chip->ctl_val[smc_write] = chip->ctl_val[smc_base] | spi_control_fill_opcode(chip->nor.program_opcode) | CONTROL_SPI_COMMAND_MODE_WRITE;
Try to improve the speed of transfers when doing DMAs Signed-off-by: Cédric Le Goater <clg@kaod.org> --- drivers/mtd/spi-nor/aspeed-smc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-)