From patchwork Tue Oct 30 10:17:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Ferre X-Patchwork-Id: 195403 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D6FC72C0097 for ; Tue, 30 Oct 2012 21:21:07 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758897Ab2J3KSk (ORCPT ); Tue, 30 Oct 2012 06:18:40 -0400 Received: from eusmtp01.atmel.com ([212.144.249.242]:37060 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758725Ab2J3KSi (ORCPT ); Tue, 30 Oct 2012 06:18:38 -0400 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.30) with Microsoft SMTP Server id 14.2.318.1; Tue, 30 Oct 2012 11:18:22 +0100 From: Nicolas Ferre To: , , CC: , , , , , , Nicolas Ferre Subject: [PATCH v3 05/10] net/macb: tx status is more than 8 bits now Date: Tue, 30 Oct 2012 11:17:57 +0100 Message-ID: <8c3727fd87fe9bd595d9e44a89982d5761166922.1351591858.git.nicolas.ferre@atmel.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: References: MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On some revision of GEM, TSR status register has more information. Signed-off-by: Nicolas Ferre --- drivers/net/ethernet/cadence/macb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index 4db52f3..cd6d431 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -314,7 +314,7 @@ static void macb_tx(struct macb *bp) status = macb_readl(bp, TSR); macb_writel(bp, TSR, status); - netdev_vdbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status); + netdev_vdbg(bp->dev, "macb_tx status = 0x%03lx\n", (unsigned long)status); if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { int i;