From patchwork Sun Feb 3 20:19:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiner Kallweit X-Patchwork-Id: 1035639 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="chBXi1Bc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43t2JM2PWSz9sDX for ; Mon, 4 Feb 2019 07:20:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727667AbfBCUUB (ORCPT ); Sun, 3 Feb 2019 15:20:01 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:43034 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727502AbfBCUT7 (ORCPT ); Sun, 3 Feb 2019 15:19:59 -0500 Received: by mail-wr1-f66.google.com with SMTP id r2so644935wrv.10 for ; Sun, 03 Feb 2019 12:19:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:from:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=U/8pAkyblDiGL8jRw2DNZgHe9gJamauSFcYqKLlRBt8=; b=chBXi1BcP4F2IDaW2q5FJBHOxTX/nhzUd02oamP08OMVDmBeX0fIvTkaaWqS5NINzc SELjo22WXikpHnkkyWYxtusrnPAH26Ai1XIif3M6eQ9S6wT1J/9s79NwaT3AxhY6lipF u6H5OEq3WIXbMnaiil/id9ZMZZRT/iucshpSeoP0kB3WlarF+I7vKo2kfJsPwRlR+rqg P4l//i83eFKSMQlYebTDxMKldGkBENKG7+AdI9sD5ccMy+I9epFKQMfqwbz3216ABHvM TU7IOrrLm/tSgUFyI+fGuYK+aWvfW8eZu1nJbIL2IKb81ZyzjwwHg2PElkVd0Q0IdNpv 88yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:references:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=U/8pAkyblDiGL8jRw2DNZgHe9gJamauSFcYqKLlRBt8=; b=jXf9Uln/stE5ETPIZvoEK2qzJdghhtJH6esK6Y4SdaIN3pz57C2IURHt9gk4l5bSwr vhw5sKCmxFGr4MeYgyXQ2cAiPztnwsBdFdMy/fePd9wl1NbXGLaM6w+SXNQnmPbaeHl2 /Xd8iw5XQSbwFYm99kOADqoe6fC0N3rD77g6AmT7G01B6HZalsBn+36TiOJVaHC8wPxy RGjkM+r0730/s6V+05xiqsGGtEWauqX7Vk4pkk/uZ6ZabU581CjeD8394mNsHvws9YL1 pbyArIozi5z54un2Mitm68xbiJjCCcp8ivMlqmK4dkp0e6BwXzAI7eMi9W4EAzWzzGG0 NAWw== X-Gm-Message-State: AJcUukc2W7rP0Pya1Wzfbt+BxMQe06wlgh6OntOZvLS4L+1yW0BUFnB5 iS7aOCeP+Xt97geBAatflhQ61k6N X-Google-Smtp-Source: ALg8bN6s4A4F+fADaSOpwlvvlSUjxTQbAUMM6pTuHE8GUUdH8QXdG9C1auvVGyisNRd+hM+cA7ka5A== X-Received: by 2002:adf:9382:: with SMTP id 2mr45736350wrp.269.1549225197198; Sun, 03 Feb 2019 12:19:57 -0800 (PST) Received: from ?IPv6:2003:ea:8bf1:e200:b082:4f91:1c1c:ad3? (p200300EA8BF1E200B0824F911C1C0AD3.dip0.t-ipconnect.de. [2003:ea:8bf1:e200:b082:4f91:1c1c:ad3]) by smtp.googlemail.com with ESMTPSA id l20sm26048922wrb.93.2019.02.03.12.19.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Feb 2019 12:19:56 -0800 (PST) Subject: [PATCH 4/4 v2 net-next] net: phy: aquantia: replace magic numbers with constants From: Heiner Kallweit To: Andrew Lunn , Florian Fainelli , David Miller Cc: "netdev@vger.kernel.org" References: Message-ID: <6bd266f7-a5f4-e1a2-58fb-0e26f3253c28@gmail.com> Date: Sun, 3 Feb 2019 21:19:06 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Replace magic numbers with proper constants. The original patch is from Andrew, I extended / adjusted certain parts: - Use decimal bit numbers. The datasheet uses hex bit numbers 0 .. F. - Order defines from highest to lowest bit numbers - correct some typos - add constant MDIO_AN_TX_VEND_INT_MASK2_LINK - Remove few functional improvements from the patch, they will come as a separate patch. Signed-off-by: Andrew Lunn Signed-off-by: Heiner Kallweit Reviewed-by: Andrew Lunn --- drivers/net/phy/aquantia.c | 80 +++++++++++++++++++++++++++++++------- 1 file changed, 66 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index fde437506..482004efa 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -19,6 +19,48 @@ #define PHY_ID_AQR107 0x03a1b4e0 #define PHY_ID_AQR405 0x03a1b4b0 +#define MDIO_AN_TX_VEND_STATUS1 0xc800 +#define MDIO_AN_TX_VEND_STATUS1_10BASET (0x0 << 1) +#define MDIO_AN_TX_VEND_STATUS1_100BASETX (0x1 << 1) +#define MDIO_AN_TX_VEND_STATUS1_1000BASET (0x2 << 1) +#define MDIO_AN_TX_VEND_STATUS1_10GBASET (0x3 << 1) +#define MDIO_AN_TX_VEND_STATUS1_2500BASET (0x4 << 1) +#define MDIO_AN_TX_VEND_STATUS1_5000BASET (0x5 << 1) +#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK (0x7 << 1) +#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) + +#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 + +#define MDIO_AN_TX_VEND_INT_MASK2 0xd401 +#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) + +/* Vendor specific 1, MDIO_MMD_VEND1 */ +#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 +#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 + +#define VEND1_GLOBAL_INT_STD_MASK 0xff00 +#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) +#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) +#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) +#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) +#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) +#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) +#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) +#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) +#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) + +#define VEND1_GLOBAL_INT_VEND_MASK 0xff01 +#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) +#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) +#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) +#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) +#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) + static int aqr_config_aneg(struct phy_device *phydev) { linkmode_copy(phydev->supported, phy_10gbit_features); @@ -32,25 +74,35 @@ static int aqr_config_intr(struct phy_device *phydev) int err; if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { - err = phy_write_mmd(phydev, MDIO_MMD_AN, 0xd401, 1); + err = phy_write_mmd(phydev, MDIO_MMD_AN, + MDIO_AN_TX_VEND_INT_MASK2, + MDIO_AN_TX_VEND_INT_MASK2_LINK); if (err < 0) return err; - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff00, 1); + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_INT_STD_MASK, + VEND1_GLOBAL_INT_STD_MASK_ALL); if (err < 0) return err; - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff01, 0x1001); + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_INT_VEND_MASK, + VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | + VEND1_GLOBAL_INT_VEND_MASK_AN); } else { - err = phy_write_mmd(phydev, MDIO_MMD_AN, 0xd401, 0); + err = phy_write_mmd(phydev, MDIO_MMD_AN, + MDIO_AN_TX_VEND_INT_MASK2, 0); if (err < 0) return err; - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff00, 0); + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_INT_STD_MASK, 0); if (err < 0) return err; - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff01, 0); + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_INT_VEND_MASK, 0); } return err; @@ -60,7 +112,8 @@ static int aqr_ack_interrupt(struct phy_device *phydev) { int reg; - reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xcc01); + reg = phy_read_mmd(phydev, MDIO_MMD_AN, + MDIO_AN_TX_VEND_INT_STATUS2); return (reg < 0) ? reg : 0; } @@ -75,21 +128,20 @@ static int aqr_read_status(struct phy_device *phydev) else phydev->link = 0; - reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xc800); + reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); mdelay(10); - reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xc800); + reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); - switch (reg) { - case 0x9: + switch (reg & MDIO_AN_TX_VEND_STATUS1_RATE_MASK) { + case MDIO_AN_TX_VEND_STATUS1_2500BASET: phydev->speed = SPEED_2500; break; - case 0x5: + case MDIO_AN_TX_VEND_STATUS1_1000BASET: phydev->speed = SPEED_1000; break; - case 0x3: + case MDIO_AN_TX_VEND_STATUS1_100BASETX: phydev->speed = SPEED_100; break; - case 0x7: default: phydev->speed = SPEED_10000; break;