From patchwork Mon Nov 17 23:06:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Cochran X-Patchwork-Id: 411857 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6821014012B for ; Tue, 18 Nov 2014 10:06:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753442AbaKQXGh (ORCPT ); Mon, 17 Nov 2014 18:06:37 -0500 Received: from mail-wi0-f179.google.com ([209.85.212.179]:64749 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753415AbaKQXGf (ORCPT ); Mon, 17 Nov 2014 18:06:35 -0500 Received: by mail-wi0-f179.google.com with SMTP id ex7so10853853wid.0 for ; Mon, 17 Nov 2014 15:06:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fz3J8JXdNPdRkR41gCMjuEv02+cEDX+CMRB+Hc6yUAc=; b=ICXhOKbIVrGDgD5dX1owJ3VwgSZjDSZTEaWuu1K2ARw6Tl5CiL8wI2tRCh3acCWMJK FWHH8DODNFIJnvYjd2HuKrGoOkE8Y0PN9JEOSzPGl5uXV7pc9ZOoQHY/IidyM9Z5BpeZ aAUX0WYoL9TK7O3Sm3RwEoUgGgcInBXu+38+Qoa9RXNJlTYL8hWjw/uOmPl+ckOae+bg 69Iwn+zQj7BMx+MEdJ1tGv6t2/qTHU2qHl0CRtpYwzfir27dBfa3/HpNYyeVhLgAAH+A 9JpH1pgM4RsklyKcyVHqXPOlhF37sHaEaeqa9O+2LcCDc3Tsrcm9VCxlV53g9ByDGMKI fpfQ== X-Received: by 10.180.210.195 with SMTP id mw3mr34208671wic.62.1416265593295; Mon, 17 Nov 2014 15:06:33 -0800 (PST) Received: from hoboy.home (62-47-209-184.adsl.highway.telekom.at. [62.47.209.184]) by mx.google.com with ESMTPSA id h8sm14196140wiy.17.2014.11.17.15.06.31 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Nov 2014 15:06:32 -0800 (PST) From: Richard Cochran To: Cc: David Miller , , Jacob Keller , Jeff Kirsher , John Ronciak , Matthew Vick Subject: [PATCH net-next 2/4] igb: do not clobber the TSAUXC bits on reset. Date: Tue, 18 Nov 2014 00:06:23 +0100 Message-Id: <5c892a6a13d120193fdbd2dd62e9604ae0d5d404.1416265321.git.richardcochran@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The TSAUXC register has a number of different bits, one of which disables the main clock function. Previously, the clock was re-enabled by clearing the entire register. This patch changes the code to preserve the values of the other bits in that register. Signed-off-by: Richard Cochran --- drivers/net/ethernet/intel/igb/igb_ptp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igb/igb_ptp.c b/drivers/net/ethernet/intel/igb/igb_ptp.c index 794c139..ce57128 100644 --- a/drivers/net/ethernet/intel/igb/igb_ptp.c +++ b/drivers/net/ethernet/intel/igb/igb_ptp.c @@ -905,6 +905,8 @@ void igb_ptp_stop(struct igb_adapter *adapter) void igb_ptp_reset(struct igb_adapter *adapter) { struct e1000_hw *hw = &adapter->hw; + unsigned long flags; + u32 tsauxc; if (!(adapter->flags & IGB_FLAG_PTP)) return; @@ -923,7 +925,11 @@ void igb_ptp_reset(struct igb_adapter *adapter) case e1000_i210: case e1000_i211: /* Enable the timer functions and interrupts. */ - wr32(E1000_TSAUXC, 0x0); + spin_lock_irqsave(&adapter->tmreg_lock, flags); + tsauxc = rd32(E1000_TSAUXC); + tsauxc &= ~TSAUXC_DISABLE; + wr32(E1000_TSAUXC, tsauxc); + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); wr32(E1000_TSIM, TSYNC_INTERRUPTS); wr32(E1000_IMS, E1000_IMS_TS); break;