diff mbox series

[net-next,4/8] r8169: improve rtl_pcie_state_l2l3_enable

Message ID 49adda3d-fbed-4d60-b5cb-b310529e4fa9@gmail.com
State Superseded
Delegated to: David Miller
Headers show
Series r8169: series with smaller improvements | expand

Commit Message

Heiner Kallweit Jan. 19, 2019, 8:49 p.m. UTC 
All calls to this function have the enable parameter set to false.
So we can replace the function with a disable-only version.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
 drivers/net/ethernet/realtek/r8169.c | 24 ++++++++----------------
 1 file changed, 8 insertions(+), 16 deletions(-)

Comments

kernel test robot Jan. 21, 2019, 2:25 p.m. UTC | #1 
Hi Heiner,

I love your patch! Yet something to improve:

[auto build test ERROR on net-next/master]

url:    https://github.com/0day-ci/linux/commits/Heiner-Kallweit/r8169-series-with-smaller-improvements/20190121-212709
config: i386-randconfig-x014-201903 (attached as .config)
compiler: gcc-8 (Debian 8.2.0-14) 8.2.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/net//ethernet/realtek/r8169.c: In function 'rtl_hw_start_8168h_1':
>> drivers/net//ethernet/realtek/r8169.c:5158:2: error: implicit declaration of function 'rtl_pcie_state_l2l3_enable'; did you mean 'rtl_pcie_state_l2l3_disable'? [-Werror=implicit-function-declaration]
     rtl_pcie_state_l2l3_enable(tp, false);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~
     rtl_pcie_state_l2l3_disable
   cc1: some warnings being treated as errors

vim +5158 drivers/net//ethernet/realtek/r8169.c

45dd95c44 hayeswang       2013-07-08  5106  
6e1d0b898 Chun-Hao Lin    2014-08-20  5107  static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6e1d0b898 Chun-Hao Lin    2014-08-20  5108  {
72521ea07 Andrzej Hajda   2015-09-24  5109  	int rg_saw_cnt;
6e1d0b898 Chun-Hao Lin    2014-08-20  5110  	u32 data;
6e1d0b898 Chun-Hao Lin    2014-08-20  5111  	static const struct ephy_info e_info_8168h_1[] = {
6e1d0b898 Chun-Hao Lin    2014-08-20  5112  		{ 0x1e, 0x0800,	0x0001 },
6e1d0b898 Chun-Hao Lin    2014-08-20  5113  		{ 0x1d, 0x0000,	0x0800 },
6e1d0b898 Chun-Hao Lin    2014-08-20  5114  		{ 0x05, 0xffff,	0x2089 },
6e1d0b898 Chun-Hao Lin    2014-08-20  5115  		{ 0x06, 0xffff,	0x5881 },
6e1d0b898 Chun-Hao Lin    2014-08-20  5116  		{ 0x04, 0xffff,	0x154a },
6e1d0b898 Chun-Hao Lin    2014-08-20  5117  		{ 0x01, 0xffff,	0x068b }
6e1d0b898 Chun-Hao Lin    2014-08-20  5118  	};
6e1d0b898 Chun-Hao Lin    2014-08-20  5119  
6e1d0b898 Chun-Hao Lin    2014-08-20  5120  	/* disable aspm and clock request before access ephy */
a99790bf5 Kai-Heng Feng   2018-06-21  5121  	rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b898 Chun-Hao Lin    2014-08-20  5122  	rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6e1d0b898 Chun-Hao Lin    2014-08-20  5123  
6e1d0b898 Chun-Hao Lin    2014-08-20  5124  	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5125  	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5126  	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5127  	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5128  
f37658da2 Heiner Kallweit 2018-06-23  5129  	rtl_set_def_aspm_entry_latency(tp);
6e1d0b898 Chun-Hao Lin    2014-08-20  5130  
8d98aa39b Heiner Kallweit 2018-04-16  5131  	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b898 Chun-Hao Lin    2014-08-20  5132  
706123d06 Chun-Hao Lin    2014-10-01  5133  	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
706123d06 Chun-Hao Lin    2014-10-01  5134  	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5135  
706123d06 Chun-Hao Lin    2014-10-01  5136  	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5137  
706123d06 Chun-Hao Lin    2014-10-01  5138  	rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5139  
6e1d0b898 Chun-Hao Lin    2014-08-20  5140  	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5141  
1ef7286e7 Andy Shevchenko 2018-03-01  5142  	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
1ef7286e7 Andy Shevchenko 2018-03-01  5143  	RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b898 Chun-Hao Lin    2014-08-20  5144  
6e1d0b898 Chun-Hao Lin    2014-08-20  5145  	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5146  	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5147  
6e1d0b898 Chun-Hao Lin    2014-08-20  5148  	/* Adjust EEE LED frequency */
1ef7286e7 Andy Shevchenko 2018-03-01  5149  	RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b898 Chun-Hao Lin    2014-08-20  5150  
1ef7286e7 Andy Shevchenko 2018-03-01  5151  	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
1ef7286e7 Andy Shevchenko 2018-03-01  5152  	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b898 Chun-Hao Lin    2014-08-20  5153  
1ef7286e7 Andy Shevchenko 2018-03-01  5154  	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b898 Chun-Hao Lin    2014-08-20  5155  
706123d06 Chun-Hao Lin    2014-10-01  5156  	rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b898 Chun-Hao Lin    2014-08-20  5157  
6e1d0b898 Chun-Hao Lin    2014-08-20 @5158  	rtl_pcie_state_l2l3_enable(tp, false);
6e1d0b898 Chun-Hao Lin    2014-08-20  5159  
6e1d0b898 Chun-Hao Lin    2014-08-20  5160  	rtl_writephy(tp, 0x1f, 0x0c42);
584933334 Chun-Hao Lin    2015-12-24  5161  	rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b898 Chun-Hao Lin    2014-08-20  5162  	rtl_writephy(tp, 0x1f, 0x0000);
6e1d0b898 Chun-Hao Lin    2014-08-20  5163  	if (rg_saw_cnt > 0) {
6e1d0b898 Chun-Hao Lin    2014-08-20  5164  		u16 sw_cnt_1ms_ini;
6e1d0b898 Chun-Hao Lin    2014-08-20  5165  
6e1d0b898 Chun-Hao Lin    2014-08-20  5166  		sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6e1d0b898 Chun-Hao Lin    2014-08-20  5167  		sw_cnt_1ms_ini &= 0x0fff;
6e1d0b898 Chun-Hao Lin    2014-08-20  5168  		data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec00 Chun-Hao Lin    2016-02-05  5169  		data &= ~0x0fff;
6e1d0b898 Chun-Hao Lin    2014-08-20  5170  		data |= sw_cnt_1ms_ini;
6e1d0b898 Chun-Hao Lin    2014-08-20  5171  		r8168_mac_ocp_write(tp, 0xd412, data);
6e1d0b898 Chun-Hao Lin    2014-08-20  5172  	}
6e1d0b898 Chun-Hao Lin    2014-08-20  5173  
6e1d0b898 Chun-Hao Lin    2014-08-20  5174  	data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec00 Chun-Hao Lin    2016-02-05  5175  	data &= ~0xf0;
a2cb7ec00 Chun-Hao Lin    2016-02-05  5176  	data |= 0x70;
6e1d0b898 Chun-Hao Lin    2014-08-20  5177  	r8168_mac_ocp_write(tp, 0xe056, data);
6e1d0b898 Chun-Hao Lin    2014-08-20  5178  
6e1d0b898 Chun-Hao Lin    2014-08-20  5179  	data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec00 Chun-Hao Lin    2016-02-05  5180  	data &= ~0x6000;
a2cb7ec00 Chun-Hao Lin    2016-02-05  5181  	data |= 0x8008;
6e1d0b898 Chun-Hao Lin    2014-08-20  5182  	r8168_mac_ocp_write(tp, 0xe052, data);
6e1d0b898 Chun-Hao Lin    2014-08-20  5183  
6e1d0b898 Chun-Hao Lin    2014-08-20  5184  	data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec00 Chun-Hao Lin    2016-02-05  5185  	data &= ~0x01ff;
6e1d0b898 Chun-Hao Lin    2014-08-20  5186  	data |= 0x017f;
6e1d0b898 Chun-Hao Lin    2014-08-20  5187  	r8168_mac_ocp_write(tp, 0xe0d6, data);
6e1d0b898 Chun-Hao Lin    2014-08-20  5188  
6e1d0b898 Chun-Hao Lin    2014-08-20  5189  	data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec00 Chun-Hao Lin    2016-02-05  5190  	data &= ~0x0fff;
6e1d0b898 Chun-Hao Lin    2014-08-20  5191  	data |= 0x047f;
6e1d0b898 Chun-Hao Lin    2014-08-20  5192  	r8168_mac_ocp_write(tp, 0xd420, data);
6e1d0b898 Chun-Hao Lin    2014-08-20  5193  
6e1d0b898 Chun-Hao Lin    2014-08-20  5194  	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6e1d0b898 Chun-Hao Lin    2014-08-20  5195  	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6e1d0b898 Chun-Hao Lin    2014-08-20  5196  	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6e1d0b898 Chun-Hao Lin    2014-08-20  5197  	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf5 Kai-Heng Feng   2018-06-21  5198  
a99790bf5 Kai-Heng Feng   2018-06-21  5199  	rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b898 Chun-Hao Lin    2014-08-20  5200  }
6e1d0b898 Chun-Hao Lin    2014-08-20  5201  

:::::: The code at line 5158 was first introduced by commit
:::::: 6e1d0b8988188956dac091441c1492a79a342666 r8169:add support for RTL8168H and RTL8107E

:::::: TO: Chun-Hao Lin <hau@realtek.com>
:::::: CC: David S. Miller <davem@davemloft.net>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox series

Patch

diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index c4d53bc6a..0bd07be8f 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -4691,18 +4691,10 @@  static void rtl_enable_clock_request(struct rtl8169_private *tp)
 				 PCI_EXP_LNKCTL_CLKREQ_EN);
 }
 
-static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
+static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
 {
-	u8 data;
-
-	data = RTL_R8(tp, Config3);
-
-	if (enable)
-		data |= Rdy_to_L23;
-	else
-		data &= ~Rdy_to_L23;
-
-	RTL_W8(tp, Config3, data);
+	/* work around an issue when PCI reset occurs during L2/L3 state */
+	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
 }
 
 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
@@ -5023,7 +5015,7 @@  static void rtl_hw_start_8411(struct rtl8169_private *tp)
 	};
 
 	rtl_hw_start_8168f(tp);
-	rtl_pcie_state_l2l3_enable(tp, false);
+	rtl_pcie_state_l2l3_disable(tp);
 
 	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
 
@@ -5057,7 +5049,7 @@  static void rtl_hw_start_8168g(struct rtl8169_private *tp)
 	rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
 	rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
 
-	rtl_pcie_state_l2l3_enable(tp, false);
+	rtl_pcie_state_l2l3_disable(tp);
 }
 
 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
@@ -5511,7 +5503,7 @@  static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
 
 	rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
 
-	rtl_pcie_state_l2l3_enable(tp, false);
+	rtl_pcie_state_l2l3_disable(tp);
 }
 
 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
@@ -5546,7 +5538,7 @@  static void rtl_hw_start_8402(struct rtl8169_private *tp)
 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
 	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
 
-	rtl_pcie_state_l2l3_enable(tp, false);
+	rtl_pcie_state_l2l3_disable(tp);
 }
 
 static void rtl_hw_start_8106(struct rtl8169_private *tp)
@@ -5560,7 +5552,7 @@  static void rtl_hw_start_8106(struct rtl8169_private *tp)
 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
 
-	rtl_pcie_state_l2l3_enable(tp, false);
+	rtl_pcie_state_l2l3_disable(tp);
 	rtl_hw_aspm_clkreq_enable(tp, true);
 }