| Message ID | 20200114164553.12997-1-m.grzeschik@pengutronix.de |
|---|---|
| State | Superseded |
| Delegated to: | David Miller |
| Headers | show |
| Series | [v2] net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset | expand |
On 14.01.2020 17:45, Michael Grzeschik wrote: > According to the Datasheet this bit should be 0 (Normal operation) in > default. With the FORCE_LINK_GOOD bit set, it is not possible to get a > link. This patch sets FORCE_LINK_GOOD to the default value after > resetting the phy. > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> > --- > v1 -> v2: - fixed typo in subject line > - used phy_modify instead of read/write > > drivers/net/phy/dp83867.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c > index adda0d0eab800..68855177d92cc 100644 > --- a/drivers/net/phy/dp83867.c > +++ b/drivers/net/phy/dp83867.c > @@ -99,6 +99,7 @@ > #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) > #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) > #define DP83867_PHYCR_RESERVED_MASK BIT(11) > +#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) > > /* RGMIIDCTL bits */ > #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf > @@ -635,6 +636,15 @@ static int dp83867_phy_reset(struct phy_device *phydev) > > usleep_range(10, 20); > > + /* After reset FORCE_LINK_GOOD bit is set. Although the > + * default value should be unset. Disable FORCE_LINK_GOOD > + * for the phy to work properly. > + */ > + err = phy_modify(phydev, MII_DP83867_PHYCTRL, > + DP83867_PHYCR_FORCE_LINK_GOOD, 0); > + if (err < 0) > + return err; > + > return 0; You can simply do "return phy_modify();" here. > } > >
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index adda0d0eab800..68855177d92cc 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -99,6 +99,7 @@ #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) #define DP83867_PHYCR_RESERVED_MASK BIT(11) +#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf @@ -635,6 +636,15 @@ static int dp83867_phy_reset(struct phy_device *phydev) usleep_range(10, 20); + /* After reset FORCE_LINK_GOOD bit is set. Although the + * default value should be unset. Disable FORCE_LINK_GOOD + * for the phy to work properly. + */ + err = phy_modify(phydev, MII_DP83867_PHYCTRL, + DP83867_PHYCR_FORCE_LINK_GOOD, 0); + if (err < 0) + return err; + return 0; }
According to the Datasheet this bit should be 0 (Normal operation) in default. With the FORCE_LINK_GOOD bit set, it is not possible to get a link. This patch sets FORCE_LINK_GOOD to the default value after resetting the phy. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> --- v1 -> v2: - fixed typo in subject line - used phy_modify instead of read/write drivers/net/phy/dp83867.c | 10 ++++++++++ 1 file changed, 10 insertions(+)