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[v3,net-next,02/11] net: phylink: make QSGMII a valid PHY mode for in-band AN

Message ID 20191227213626.4404-3-olteanv@gmail.com
State Changes Requested
Delegated to: David Miller
Headers show
Series Convert Felix DSA switch to PHYLINK | expand

Commit Message

Vladimir Oltean Dec. 27, 2019, 9:36 p.m. UTC 
From: Vladimir Oltean <vladimir.oltean@nxp.com>

QSGMII is a SerDes protocol clocked at 5 Gbaud (4 times higher than
SGMII which is clocked at 1.25 Gbaud), with the same 8b/10b encoding and
some extra symbols for synchronization. Logically it offers 4 SGMII
interfaces multiplexed onto the same physical lanes. Each MAC PCS has
its own in-band AN process with the system side of the QSGMII PHY, which
is identical to the regular SGMII AN process.

So allow QSGMII as a valid in-band AN mode, since it is no different
from software perspective from regular SGMII.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Changes in v3:
- None.

 drivers/net/phy/phylink.c | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index ba9468cc8e13..c19cbcf183e6 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -281,6 +281,7 @@  static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
 
 		switch (pl->link_config.interface) {
 		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_QSGMII:
 			phylink_set(pl->supported, 10baseT_Half);
 			phylink_set(pl->supported, 10baseT_Full);
 			phylink_set(pl->supported, 100baseT_Half);