| Message ID | 20191227005954.25268-1-olteanv@gmail.com |
|---|---|
| State | Accepted |
| Delegated to: | David Miller |
| Headers | show |
| Series | [net] net: dsa: sja1105: Take PTP egress timestamp by port, not mgmt slot | expand |
From: Vladimir Oltean <olteanv@gmail.com> Date: Fri, 27 Dec 2019 02:59:54 +0200 > The PTP egress timestamp N must be captured from register PTPEGR_TS[n], > where n = 2 * PORT + TSREG. There are 10 PTPEGR_TS registers, 2 per > port. We are only using TSREG=0. > > As opposed to the management slots, which are 4 in number > (SJA1105_NUM_PORTS, minus the CPU port). Any management frame (which > includes PTP frames) can be sent to any non-CPU port through any > management slot. When the CPU port is not the last port (#4), there will > be a mismatch between the slot and the port number. > > Luckily, the only mainline occurrence with this switch > (arch/arm/boot/dts/ls1021a-tsn.dts) does have the CPU port as #4, so the > issue did not manifest itself thus far. > > Fixes: 47ed985e97f5 ("net: dsa: sja1105: Add logic for TX timestamping") > Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Applied, thanks.
diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja1105/sja1105_main.c index 3e9bd205d91a..73649c99d5a5 100644 --- a/drivers/net/dsa/sja1105/sja1105_main.c +++ b/drivers/net/dsa/sja1105/sja1105_main.c @@ -1952,7 +1952,7 @@ static netdev_tx_t sja1105_port_deferred_xmit(struct dsa_switch *ds, int port, if (!clone) goto out; - sja1105_ptp_txtstamp_skb(ds, slot, clone); + sja1105_ptp_txtstamp_skb(ds, port, clone); out: mutex_unlock(&priv->mgmt_lock); diff --git a/drivers/net/dsa/sja1105/sja1105_ptp.c b/drivers/net/dsa/sja1105/sja1105_ptp.c index 68d8c3440c46..56f18ff60a41 100644 --- a/drivers/net/dsa/sja1105/sja1105_ptp.c +++ b/drivers/net/dsa/sja1105/sja1105_ptp.c @@ -655,7 +655,7 @@ void sja1105_ptp_clock_unregister(struct dsa_switch *ds) ptp_data->clock = NULL; } -void sja1105_ptp_txtstamp_skb(struct dsa_switch *ds, int slot, +void sja1105_ptp_txtstamp_skb(struct dsa_switch *ds, int port, struct sk_buff *skb) { struct sja1105_private *priv = ds->priv; @@ -673,7 +673,7 @@ void sja1105_ptp_txtstamp_skb(struct dsa_switch *ds, int slot, goto out; } - rc = sja1105_ptpegr_ts_poll(ds, slot, &ts); + rc = sja1105_ptpegr_ts_poll(ds, port, &ts); if (rc < 0) { dev_err(ds->dev, "timed out polling for tstamp\n"); kfree_skb(skb);
The PTP egress timestamp N must be captured from register PTPEGR_TS[n], where n = 2 * PORT + TSREG. There are 10 PTPEGR_TS registers, 2 per port. We are only using TSREG=0. As opposed to the management slots, which are 4 in number (SJA1105_NUM_PORTS, minus the CPU port). Any management frame (which includes PTP frames) can be sent to any non-CPU port through any management slot. When the CPU port is not the last port (#4), there will be a mismatch between the slot and the port number. Luckily, the only mainline occurrence with this switch (arch/arm/boot/dts/ls1021a-tsn.dts) does have the CPU port as #4, so the issue did not manifest itself thus far. Fixes: 47ed985e97f5 ("net: dsa: sja1105: Add logic for TX timestamping") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> --- This patch will not apply to stable trees due to refactoring commit a9d6ed7a8bd0 ("net: dsa: sja1105: Move PTP data to its own private structure"). drivers/net/dsa/sja1105/sja1105_main.c | 2 +- drivers/net/dsa/sja1105/sja1105_ptp.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)