| Message ID | 20191226190101.3766479-2-martin.blumenstingl@googlemail.com |
|---|---|
| State | Accepted |
| Delegated to: | David Miller |
| Headers | show |
| Series | dwmac-meson8b: Ethernet RGMII TX delay fix | expand |
On Thu, Dec 26, 2019 at 08:01:01PM +0100, Martin Blumenstingl wrote: > GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for > the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate > can be adjusted at runtime. > > So far we have been running MPLL2 with ~250MHz (and the internal > m250_div with value 1), which worked enough that we could transfer data > with an TX delay of 4ns. Unfortunately there is high packet loss with > an RGMII PHY when transferring data (receiving data works fine though). > Odroid-C1's u-boot is running with a TX delay of only 2ns as well as > the internal m250_div set to 2 - no lost (TX) packets can be observed > with that setting in u-boot. > > Manual testing has shown that the TX packet loss goes away when using > the following settings in Linux (the vendor kernel uses the same > settings): > - MPLL2 clock set to ~500MHz > - m250_div set to 2 > - TX delay set to 2ns on the MAC side > > Update the m250_div divider settings to only accept dividers greater or > equal 2 to fix the TX delay generated by the MAC. > > iperf3 results before the change: > [ ID] Interval Transfer Bitrate Retr > [ 5] 0.00-10.00 sec 182 MBytes 153 Mbits/sec 514 sender > [ 5] 0.00-10.00 sec 182 MBytes 152 Mbits/sec receiver > > iperf3 results after the change (including an updated TX delay of 2ns): > [ ID] Interval Transfer Bitrate Retr Cwnd > [ 5] 0.00-10.00 sec 927 MBytes 778 Mbits/sec 0 sender > [ 5] 0.00-10.01 sec 927 MBytes 777 Mbits/sec receiver > > Fixes: 4f6a71b84e1afd ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration") > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: Thu, 26 Dec 2019 20:01:01 +0100 > GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for > the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate > can be adjusted at runtime. > > So far we have been running MPLL2 with ~250MHz (and the internal > m250_div with value 1), which worked enough that we could transfer data > with an TX delay of 4ns. Unfortunately there is high packet loss with > an RGMII PHY when transferring data (receiving data works fine though). > Odroid-C1's u-boot is running with a TX delay of only 2ns as well as > the internal m250_div set to 2 - no lost (TX) packets can be observed > with that setting in u-boot. > > Manual testing has shown that the TX packet loss goes away when using > the following settings in Linux (the vendor kernel uses the same > settings): > - MPLL2 clock set to ~500MHz > - m250_div set to 2 > - TX delay set to 2ns on the MAC side > > Update the m250_div divider settings to only accept dividers greater or > equal 2 to fix the TX delay generated by the MAC. > > iperf3 results before the change: > [ ID] Interval Transfer Bitrate Retr > [ 5] 0.00-10.00 sec 182 MBytes 153 Mbits/sec 514 sender > [ 5] 0.00-10.00 sec 182 MBytes 152 Mbits/sec receiver > > iperf3 results after the change (including an updated TX delay of 2ns): > [ ID] Interval Transfer Bitrate Retr Cwnd > [ 5] 0.00-10.00 sec 927 MBytes 778 Mbits/sec 0 sender > [ 5] 0.00-10.01 sec 927 MBytes 777 Mbits/sec receiver > > Fixes: 4f6a71b84e1afd ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration") > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Applied and queued up for -stable, thanks.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index bd6c01004913..0e2fa14f1423 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -112,6 +112,14 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) struct device *dev = dwmac->dev; const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS]; struct meson8b_dwmac_clk_configs *clk_configs; + static const struct clk_div_table div_table[] = { + { .div = 2, .val = 2, }, + { .div = 3, .val = 3, }, + { .div = 4, .val = 4, }, + { .div = 5, .val = 5, }, + { .div = 6, .val = 6, }, + { .div = 7, .val = 7, }, + }; clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL); if (!clk_configs) @@ -146,9 +154,9 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0; clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; - clk_configs->m250_div.flags = CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ALLOW_ZERO | - CLK_DIVIDER_ROUND_CLOSEST; + clk_configs->m250_div.table = div_table; + clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO | + CLK_DIVIDER_ROUND_CLOSEST; clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1, &clk_divider_ops, &clk_configs->m250_div.hw);
GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate can be adjusted at runtime. So far we have been running MPLL2 with ~250MHz (and the internal m250_div with value 1), which worked enough that we could transfer data with an TX delay of 4ns. Unfortunately there is high packet loss with an RGMII PHY when transferring data (receiving data works fine though). Odroid-C1's u-boot is running with a TX delay of only 2ns as well as the internal m250_div set to 2 - no lost (TX) packets can be observed with that setting in u-boot. Manual testing has shown that the TX packet loss goes away when using the following settings in Linux (the vendor kernel uses the same settings): - MPLL2 clock set to ~500MHz - m250_div set to 2 - TX delay set to 2ns on the MAC side Update the m250_div divider settings to only accept dividers greater or equal 2 to fix the TX delay generated by the MAC. iperf3 results before the change: [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 182 MBytes 153 Mbits/sec 514 sender [ 5] 0.00-10.00 sec 182 MBytes 152 Mbits/sec receiver iperf3 results after the change (including an updated TX delay of 2ns): [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-10.00 sec 927 MBytes 778 Mbits/sec 0 sender [ 5] 0.00-10.01 sec 927 MBytes 777 Mbits/sec receiver Fixes: 4f6a71b84e1afd ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-)