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bh=45PGGGQvCnyFHHkBSTgwjPbefCeAe5O1Vi1OQyqVUAw=; b=O1oHgMKCDvfBM5lp/iLFsXX2iYOcj0Tp1+J39JTz1glwDhclMnzDLtglJZaPL0GTzO BaWA9Z+lloPQWMq5y9XPEmQngyElHy9rg+Ece9G6JXbn9MvzCvKImf90NEr3YpqSYISj 9MuS8D+A54SgLJbxdUN2qqIvSwSR5n13kbZ0HbGkp7KA0f/NapLkp0RAccJ+wOH73hOY YdryN2IDnpAOl1WuQDj3RLtvDNv5ZoxwMBF7iRlRAdFsfZTnWRMB2dM+OyFW1L3zQoLb W9kmzemSipBEMglLQQr7niDfbd4L4OxiIOOvRs1xt9UoaBP6EPHKhHwxY09sIkFhQNgj frjA== X-Gm-Message-State: APjAAAULNqfpXHyS5HkdvFdYWVfj+6gFAXFhHxrFCHhfSk7zypEGHYct +jBy6AEd7gE75+3P1BYEzss= X-Google-Smtp-Source: APXvYqz3dKmIKbX+1MAf4L2cpbgjqwtmwbH1FjaGE3auWi0o8rPdEts+Vvr7XKoY+gJvHxdcvw8w7w== X-Received: by 2002:a1c:f205:: with SMTP id s5mr1439943wmc.124.1553397920642; Sat, 23 Mar 2019 20:25:20 -0700 (PDT) Received: from localhost.localdomain ([188.26.228.227]) by smtp.gmail.com with ESMTPSA id c20sm12243049wre.28.2019.03.23.20.25.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Mar 2019 20:25:20 -0700 (PDT) From: Vladimir Oltean To: davem@davemloft.net, netdev@vger.kernel.org Cc: f.fainelli@gmail.com, andrew@lunn.ch, vivien.didelot@gmail.com, linus.walleij@linaro.org, Vladimir Oltean Subject: [RFC PATCH net-next 12/13] Documentation: networking: dsa: Add details about NXP SJA1105 driver Date: Sun, 24 Mar 2019 05:23:45 +0200 Message-Id: <20190324032346.32394-13-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190324032346.32394-1-olteanv@gmail.com> References: <20190324032346.32394-1-olteanv@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Signed-off-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- Documentation/networking/dsa/sja1105.txt | 83 ++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/networking/dsa/sja1105.txt diff --git a/Documentation/networking/dsa/sja1105.txt b/Documentation/networking/dsa/sja1105.txt new file mode 100644 index 000000000000..b6f2c1bedd02 --- /dev/null +++ b/Documentation/networking/dsa/sja1105.txt @@ -0,0 +1,83 @@ +NXP SJA1105 switch driver +========================= + +The NXP SJA1105 is a family of 6 devices: +* SJA1105E: First generation, no TTEthernet +* SJA1105T: First generation, TTEthernet +* SJA1105P: Second generation, no TTEthernet, no SGMII +* SJA1105Q: Second generation, TTEthernet, no SGMII +* SJA1105R: Second generation, no TTEthernet, SGMII +* SJA1105S: Second generation, TTEthernet, SGMII + +These are SPI-managed automotive switches, with all ports being gigabit +capable, and supporting MII/RMII/RGMII and optionally SGMII on one port. + +The switches do not have an MDIO bus of their own and do not support +in-band autonegotiation, so for proper PHY management, the host's MDIO +bus controller needs to be used. + +Being automotive parts, their configuration interface is geared towards +set-and-forget use, with minimal dynamic interaction at runtime. They +require a static configuration to be composed by software and packed +with CRC and table headers, and sent over SPI. + +The static configuration is composed of several configuration tables. Each +table takes a number of entries. Some configuration tables can be (partially) +reconfigured at runtime, some not. Some tables are mandatory, some not. + +Table | Mandatory | Reconfigurable +-----------------------------+------------------+----------------------------- +Schedule | no | no +Schedule entry points | if Scheduling | no +VL Lookup | no | no +VL Policing | if VL Lookup | no +VL Forwarding | if VL Lookup | no +L2 Lookup | no | no +L2 Policing | yes | no +VLAN Lookup | yes | yes +L2 Forwarding | yes | partially (fully on P/Q/R/S) +MAC Config | yes | partially (fully on P/Q/R/S) +Schedule Params | if Scheduling | no +Schedule Entry Points Params | if Scheduling | no +VL Forwarding Params | if VL Forwarding | no +L2 Lookup Params | no | partially (fully on P/Q/R/S) +L2 Forwarding Params | yes | no +Clock Sync Params | no | no +AVB Params | no | no +General Params | yes | partially +Retagging | no | yes +xMII Params | yes | no +SGMII | no | yes + +Also the configuration is write-only (software cannot read it back from the +switch except for very few exceptions). + +So the driver creates the static configuration at probe time, and keeps it at +all times in memory, as a shadow for the hardware state. When required to +change a hardware setting, the static configuration is also updated. +If that changed setting can be transmitted to the switch through the dynamic +reconfiguration interface, it is; otherwise the switch is reset and +reprogrammed with the updated static configuration. + +The switches do not support switch tagging in hardware. But they do support +customizing the TPID by which VLAN traffic is identified as such. The switch +driver is leveraging CONFIG_NET_DSA_TAG_8021Q by requesting that special VLANs +(with a custom TPID of ETH_P_EDSA instead of ETH_P_8021Q) are installed on its +ports when not in vlan_filtering mode. This does not interfere with the +reception and transmission of real 802.1Q-tagged traffic, because the switch +does no longer parse those packets as VLAN after the TPID change. +The TPID is restored when vlan_filtering is requested, and IP termination +becomes no longer possible through the switch netdevices in this mode. + +The switches have two programmable filters for link-local destination MACs. +These are used to trap BPDUs and PTP traffic to the master netdevice, and are +further used to support STP and 1588 ordinary clock/boundary clock +functionality. + +Among other notable features, the switches have a PTP Hardware Clock that can +be steered through SPI and used for timestamping on ingress and egress. +Also, the T, Q and S devices support TTEthernet (an implementation of +SAE AS6802 from TTTech), which is a set of Ethernet QoS enhancements similar in +behavior to IEEE TSN. Configuring these features is currently not supported in +the driver. +