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Tue, 5 Feb 2019 10:05:34 +0000 From: Pankaj Bansal To: Andrew Lunn , Florian Fainelli CC: "netdev@vger.kernel.org" , Pankaj Bansal Subject: [PATCH v3 1/2] dt-bindings: net: add MDIO bus multiplexer driven by a regmap device Thread-Topic: [PATCH v3 1/2] dt-bindings: net: add MDIO bus multiplexer driven by a regmap device Thread-Index: AQHUvTpVElXPoo9VjEuW638DtcinZw== Date: Tue, 5 Feb 2019 10:05:33 +0000 Message-ID: <20190205153014.3807-2-pankaj.bansal@nxp.com> References: <20190205153014.3807-1-pankaj.bansal@nxp.com> In-Reply-To: <20190205153014.3807-1-pankaj.bansal@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::27) To VI1PR0401MB2496.eurprd04.prod.outlook.com (2603:10a6:800:56::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pankaj.bansal@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [92.120.1.69] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: lTLVmL8ViqLZjAe+o62wm7RofyL7qhGKQ98KH9BGrhSjuXbcaEopHgT746a7sHOZ4kuFm4N125p2cLMuC/RvA8Esf1fVWLYJsXrlnFip+1GZt42UmdsPYmpQ0ycuNcwJEaZBWt4RjYWnx0cNjOQlQ8jLt6tols9h2zm0Bxiswpwv2dwZ+48tNnkoIjnITo86IiHoPtTpt5RtFDGCngwcjNXT9eyolSJtTTYOEP8Civ+HVvdTlZpFjZryjEgCHZ9ciMQDm900dEzy7tloY/cITf2LbMI93YlzGJdJ53/HHrbnBCg2of/8Rj/beYkouExdCMuoR2DLoaxTb8WedEewFLnSMo1Zd9BcEg55EaAT+o7vHmzqUx8ddV+S9KmUhD8r9PU8kfM/c6qnUGBHBnBI2dXDUR6D7xvmeXY8IquaoV4= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf606ecf-1c02-4679-03e4-08d68b5177b6 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Feb 2019 10:05:32.7535 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2526 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for an MDIO bus multiplexer controlled by a regmap device, like an FPGA. Tested on a NXP LX2160AQDS board which uses the "QIXIS" FPGA attached to the i2c bus. Signed-off-by: Pankaj Bansal --- Notes: V3: - No change V2: - New file describing the device tree bindings for regmap controlled devices' mdio mux .../bindings/net/mdio-mux-regmap.txt | 167 +++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mdio-mux-regmap.txt b/Documentation/devicetree/bindings/net/mdio-mux-regmap.txt new file mode 100644 index 000000000000..8968f317965f --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux-regmap.txt @@ -0,0 +1,167 @@ +Properties for an MDIO bus multiplexer controlled by a regmap + +This is a special case of a MDIO bus multiplexer. A regmap device, +like an FPGA, is used to control which child bus is connected. The mdio-mux +node must be a child of the device that is controlled by a regmap. +The driver currently only supports devices with upto 32-bit registers. + +Required properties in addition to the generic multiplexer properties: + +- reg : integer, contains the offset of the register that controls the bus + multiplexer. it can be 32 bit number. + +- mux-mask : integer, contains an 32 bit mask that specifies which + bits in the register control the actual bus multiplexer. The + 'reg' property of each child mdio-mux node must be constrained by + this mask. + +Example 1: + +The FPGA node defines a i2c connected FPGA with a register space of 0x30 bytes. +For the "EMI2" MDIO bus, register 0x54 (BRDCFG4) controls the mux on that bus. +A bitmask of 0x07 means that bits 0, 1 and 2 (bit 0 is lsb) are the bits on +BRDCFG4 that control the actual mux. + +i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + fsl-scl-gpio = <&gpio2 15 0>; + status = "okay"; + + /* The FPGA node */ + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c"; + reg = <0x66>; // fpga device address on i2c bus + #address-cells = <1>; + #size-cells = <0>; + + mdio-mux-2@54 { + mdio-parent-bus = <&emdio2>; /* MDIO bus */ + reg = <0x54>; /* BRDCFG4 */ + mux-mask = <0x07>; /* EMI2_MDIO */ + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { // Slot 1 + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@@1 { + reg = <1>; + compatible = "ethernet-phy-id0210.7441"; + }; + + ethernet-phy@@0 { + reg = <0>; + compatible = "ethernet-phy-id0210.7441"; + }; + }; + + mdio@1 { // Slot 2 + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + mdio@2 { // Slot 3 + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + + }; + }; + }; +}; + +/* The parent MDIO bus. */ +emdio2: mdio@0x8B97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + little-endian; +}; + +Example 2: + +The FPGA node defines a memory mapped FPGA with a register space of 0x100 bytes. +For the "EMI1" MDIO bus, register 0x54 (BRDCFG4) controls the mux on that bus. +A bitmask of 0xe0 means that bits 5, 6 and 7 (bit 0 is lsb) are the bits on +BRDCFG4 that control the actual mux. + +ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = ; + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + /* The FPGA node */ + fpga: board-control@3,0 { + compatible = "fsl,ls1021aqds-fpga", "fsl,fpga-qixis"; + reg = <0x3 0x0 0x0000100>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-mux-1@54 { + mdio-parent-bus = <&emdio1>; /* MDIO bus */ + reg = <0x54>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { // Onboard PHYs rgmii_phy1 + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; + + mdio@20 { // Onboard PHYs rgmii_phy2 + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; + + mdio@40 { // Onboard PHYs rgmii_phy3 + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + }; +}; + +/* The parent MDIO bus. */ +emdio1: mdio@2d24000 { + compatible = "gianfar"; + device_type = "mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2d24000 0x0 0x4000>, + <0x0 0x2d10030 0x0 0x4>; +};