From patchwork Thu Dec 20 01:06:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1016438 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Ktrt6bVsz9sBh for ; Thu, 20 Dec 2018 12:07:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730693AbeLTBHJ (ORCPT ); Wed, 19 Dec 2018 20:07:09 -0500 Received: from mail-out.m-online.net ([212.18.0.9]:54228 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728468AbeLTBHB (ORCPT ); Wed, 19 Dec 2018 20:07:01 -0500 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 43Ktrg3JVdz1qvTT; Thu, 20 Dec 2018 02:06:59 +0100 (CET) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 43Ktrg38lZz1qqkr; Thu, 20 Dec 2018 02:06:59 +0100 (CET) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id Ba97mk-Me1C5; Thu, 20 Dec 2018 02:06:58 +0100 (CET) X-Auth-Info: LrqzxF2VcVmpqQTDykJpiqbMev16sWJYZgY5ELBjmhE= Received: from kurokawa.lan (ip-86-49-110-70.net.upcbroadband.cz [86.49.110.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 20 Dec 2018 02:06:58 +0100 (CET) From: Marek Vasut To: netdev@vger.kernel.org Cc: f.fainelli@gmail.com, andrew@lunn.ch, Marek Vasut , Tristram Ha , Woojung Huh Subject: [RFT][PATCH 5/7] net: dsa: microchip: Factor out register access opcode generation Date: Thu, 20 Dec 2018 02:06:45 +0100 Message-Id: <20181220010647.4059-6-marex@denx.de> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181220010647.4059-1-marex@denx.de> References: <20181220010647.4059-1-marex@denx.de> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Factor out the code which sends out the register read/write opcodes to the switch, since the code differs in single bit between read and write. Signed-off-by: Marek Vasut Cc: Andrew Lunn Cc: Florian Fainelli Cc: Tristram Ha Cc: Woojung Huh --- drivers/net/dsa/microchip/ksz9477_spi.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz9477_spi.c b/drivers/net/dsa/microchip/ksz9477_spi.c index 69baf9677def..4fc36dc2195a 100644 --- a/drivers/net/dsa/microchip/ksz9477_spi.c +++ b/drivers/net/dsa/microchip/ksz9477_spi.c @@ -25,19 +25,24 @@ /* Enough to read all switch port registers. */ #define SPI_TX_BUF_LEN 0x100 -static int ksz9477_spi_read_reg(struct spi_device *spi, u32 reg, u8 *val, - unsigned int len) +static u32 ksz9477_spi_cmd(u32 reg, bool read) { u32 txbuf; - int ret; txbuf = reg & SPI_ADDR_MASK; - txbuf |= KS_SPIOP_RD << SPI_ADDR_SHIFT; + txbuf |= (read ? KS_SPIOP_RD : KS_SPIOP_WR) << SPI_ADDR_SHIFT; txbuf <<= SPI_TURNAROUND_SHIFT; txbuf = cpu_to_be32(txbuf); - ret = spi_write_then_read(spi, &txbuf, 4, val, len); - return ret; + return txbuf; +} + +static int ksz9477_spi_read_reg(struct spi_device *spi, u32 reg, u8 *val, + unsigned int len) +{ + u32 txbuf = ksz9477_spi_cmd(reg, true); + + return spi_write_then_read(spi, &txbuf, 4, val, len); } static int ksz9477_spi_write_reg(struct spi_device *spi, u32 reg, u8 *val, @@ -45,10 +50,7 @@ static int ksz9477_spi_write_reg(struct spi_device *spi, u32 reg, u8 *val, { u32 *txbuf = (u32 *)val; - *txbuf = reg & SPI_ADDR_MASK; - *txbuf |= (KS_SPIOP_WR << SPI_ADDR_SHIFT); - *txbuf <<= SPI_TURNAROUND_SHIFT; - *txbuf = cpu_to_be32(*txbuf); + *txbuf = ksz9477_spi_cmd(reg, false); return spi_write(spi, txbuf, 4 + len); }