From patchwork Fri Jun 2 23:40:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 770641 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wfgkl1R9Xz9s3T for ; Sat, 3 Jun 2017 09:43:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751185AbdFBXnJ (ORCPT ); Fri, 2 Jun 2017 19:43:09 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:33519 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750971AbdFBXnI (ORCPT ); Fri, 2 Jun 2017 19:43:08 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 067C0A1CCE29B; Sat, 3 Jun 2017 00:43:02 +0100 (IST) Received: from localhost (10.20.1.33) by hhmail02.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Sat, 3 Jun 2017 00:43:06 +0100 From: Paul Burton To: CC: Tobias Klauser , "David S . Miller" , Jarod Wilson , , Eric Dumazet , Paul Burton Subject: [PATCH v3 5/7] net: pch_gbe: Always reset PHY along with MAC Date: Fri, 2 Jun 2017 16:40:40 -0700 Message-ID: <20170602234042.22782-6-paul.burton@imgtec.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170602234042.22782-1-paul.burton@imgtec.com> References: <20170602234042.22782-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.20.1.33] Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On the MIPS Boston development board, the EG20T MAC does not report receiving the RX clock from the (RGMII) RTL8211E PHY unless the PHY is reset at the same time as the MAC. Since the pch_gbe driver resets the MAC a number of times - twice during probe, and when taking down the network interface - we need to reset the PHY at all the same times. Do that from pch_gbe_mac_reset_hw which is used to reset the MAC in all cases. Signed-off-by: Paul Burton Cc: David S. Miller Cc: Eric Dumazet Cc: Jarod Wilson Cc: Tobias Klauser Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in v3: None Changes in v2: None drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c index 59a42c20d433..f8791be7b3b5 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c @@ -380,10 +380,13 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) { /* Read the MAC address. and store to the private data */ pch_gbe_mac_read_mac_addr(hw); + pch_gbe_phy_set_reset(hw, 1); iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET); #ifdef PCH_GBE_MAC_IFOP_RGMII iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); #endif + pch_gbe_phy_set_reset(hw, 0); + usleep_range(1250, 1500); pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); /* Setup the receive addresses */ pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);