From patchwork Mon Jan 30 04:30:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 721260 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vBc0307DCz9t0C for ; Mon, 30 Jan 2017 15:30:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="spjNdn6f"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751946AbdA3Eao (ORCPT ); Sun, 29 Jan 2017 23:30:44 -0500 Received: from mail-qk0-f195.google.com ([209.85.220.195]:36268 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751910AbdA3Eaj (ORCPT ); Sun, 29 Jan 2017 23:30:39 -0500 Received: by mail-qk0-f195.google.com with SMTP id i34so14595520qkh.3 for ; Sun, 29 Jan 2017 20:30:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u92YRLbRusaiqs+kXHTY3VSg5NMsMH0mFrENtUT8JuU=; b=spjNdn6fMMg9NIM+V0jPvQtICZSve/NSsQ3WzjVThqT43QYOB5tr70CHcaPkN9eUbl YQvrjfA+ULdREeZPEEfQHO4zWwYLCI9xGcym7MpMt5lu1kLX8nRS5NaxEcHYJSQDIDsI OALe+7Epyqd7P/05o7xsk70vco3jifjOqpZJTW1IHtd8Ekt92nm2+lYo+doJxlqcv8hV D0x5Q0UxXWMu0SWJRNhHlBTlk4mu99b+G3oDH97tzktajZZE50ISOZh3T9ic6ffFnWSL AM69/wE62D0V2e33ySEAIZ8Mhg4plA6sCGzDebZ9BYSTTxyCzjEJwfEC9RYSqcTnSr+B fyww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u92YRLbRusaiqs+kXHTY3VSg5NMsMH0mFrENtUT8JuU=; b=uaYLZRp0dwEBgaMYRJZwYH50KK4fcyRlSka6U3mheennKIhoawDH+UBLIrmlX3Vd5L 9qLuBIe/9E9zNDoLZ4A8xklz9tHHW7iSriM0SGPKlVXe1zaWg3+svahW1sJYfcOWgs97 plbkQluHIku5cSW1HJiu6rQCrzvKlEyoF2TzWk4sdrYfOPfetUgoeoDVAIgFYbx1sGUM kr/EmY+jCsTlpU/YmEb4jL5F6kxc538qJQKiNCIonoPLzNDyiUmFW6ou71UXQixpdhQy t4dXMkUjl9XATM0VxDFi/WYsdzcVGFj75vnYvGH4mRpgqhpTJtYiupQlGkVuGkpqZOkT 9BwQ== X-Gm-Message-State: AIkVDXLL3yhx6eFWzGvsz7ZyAJFwPKtS0atGU7+JdeE521bipR43kwQgrnQBxd429VwcQw== X-Received: by 10.55.204.25 with SMTP id r25mr21333108qki.213.1485750637883; Sun, 29 Jan 2017 20:30:37 -0800 (PST) Received: from fainelli-laptop.vpn.broadcom.net ([2001:470:d:73f:c1bf:596d:f44e:5a90]) by smtp.gmail.com with ESMTPSA id u49sm11120490qtc.44.2017.01.29.20.30.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Jan 2017 20:30:37 -0800 (PST) From: Florian Fainelli To: netdev@vger.kernel.org Cc: davem@davemloft.net, andrew@lunn.ch, vivien.didelot@savoirfairelinux.com, cphealy@gmail.com, jiri@mellanox.com, Florian Fainelli Subject: [PATCH net-next v4 2/4] net: dsa: b53: Add mirror capture register definitions Date: Sun, 29 Jan 2017 20:30:24 -0800 Message-Id: <20170130043026.28867-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170130043026.28867-1-f.fainelli@gmail.com> References: <20170130043026.28867-1-f.fainelli@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add definitions for the different Roboswitch registers relevant for ingress and egress mirroring. Signed-off-by: Florian Fainelli --- drivers/net/dsa/b53/b53_regs.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h index dac0af4e2cd0..9fd24c418fa4 100644 --- a/drivers/net/dsa/b53/b53_regs.h +++ b/drivers/net/dsa/b53/b53_regs.h @@ -206,6 +206,38 @@ #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ +/* Mirror capture control register (16 bit) */ +#define B53_MIR_CAP_CTL 0x10 +#define CAP_PORT_MASK 0xf +#define BLK_NOT_MIR BIT(14) +#define MIRROR_EN BIT(15) + +/* Ingress mirror control register (16 bit) */ +#define B53_IG_MIR_CTL 0x12 +#define MIRROR_MASK 0x1ff +#define DIV_EN BIT(13) +#define MIRROR_FILTER_MASK 0x3 +#define MIRROR_FILTER_SHIFT 14 +#define MIRROR_ALL 0 +#define MIRROR_DA 1 +#define MIRROR_SA 2 + +/* Ingress mirror divider register (16 bit) */ +#define B53_IG_MIR_DIV 0x14 +#define IN_MIRROR_DIV_MASK 0x3ff + +/* Ingress mirror MAC address register (48 bit) */ +#define B53_IG_MIR_MAC 0x16 + +/* Egress mirror control register (16 bit) */ +#define B53_EG_MIR_CTL 0x1C + +/* Egress mirror divider register (16 bit) */ +#define B53_EG_MIR_DIV 0x1E + +/* Egress mirror MAC address register (48 bit) */ +#define B53_EG_MIR_MAC 0x20 + /* Device ID register (8 or 32 bit) */ #define B53_DEVICE_ID 0x30