From patchwork Fri Mar 20 16:50:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Lendacky X-Patchwork-Id: 452713 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 37ECC14019D for ; Sat, 21 Mar 2015 03:51:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752089AbbCTQu0 (ORCPT ); Fri, 20 Mar 2015 12:50:26 -0400 Received: from mail-bl2on0133.outbound.protection.outlook.com ([65.55.169.133]:54272 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751516AbbCTQuV (ORCPT ); Fri, 20 Mar 2015 12:50:21 -0400 Received: from BY2PR02CA0063.namprd02.prod.outlook.com (10.242.32.21) by DM2PR02MB416.namprd02.prod.outlook.com (10.141.86.152) with Microsoft SMTP Server (TLS) id 15.1.112.16; Fri, 20 Mar 2015 16:50:19 +0000 Received: from BY2FFO11FD055.protection.gbl (2a01:111:f400:7c0c::170) by BY2PR02CA0063.outlook.office365.com (2a01:111:e400:2c2a::21) with Microsoft SMTP Server (TLS) id 15.1.118.21 via Frontend Transport; Fri, 20 Mar 2015 16:50:19 +0000 Received: from atltwp02.amd.com (165.204.84.222) by BY2FFO11FD055.mail.protection.outlook.com (10.1.15.192) with Microsoft SMTP Server id 15.1.112.13 via Frontend Transport; Fri, 20 Mar 2015 16:50:18 +0000 X-WSS-ID: 0NLIS3S-08-4AL-02 X-M-MSG: Received: from satlvexedge02.amd.com (satlvexedge02.amd.com [10.177.96.29]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp02.amd.com (Axway MailGate 5.3.1) with ESMTPS id 26198D16033; Fri, 20 Mar 2015 11:50:16 -0500 (CDT) Received: from SATLEXDAG01.amd.com (10.181.40.3) by SATLVEXEDGE02.amd.com (10.177.96.29) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 20 Mar 2015 11:50:23 -0500 Received: from tlendack-t1.amdoffice.net (10.180.168.240) by SATLEXDAG01.amd.com (10.181.40.3) with Microsoft SMTP Server id 14.3.195.1; Fri, 20 Mar 2015 12:50:16 -0400 Subject: [PATCH net-next v3 5/9] amd-xgbe: Use the new DMA memory barriers where appropriate From: Tom Lendacky To: CC: David Miller Date: Fri, 20 Mar 2015 11:50:16 -0500 Message-ID: <20150320165016.13799.49326.stgit@tlendack-t1.amdoffice.net> In-Reply-To: <20150320164936.13799.13796.stgit@tlendack-t1.amdoffice.net> References: <20150320164936.13799.13796.stgit@tlendack-t1.amdoffice.net> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-EOPAttributedMessage: 0 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=Thomas.Lendacky@amd.com; davemloft.net; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:165.204.84.222; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(77096005)(83506001)(77156002)(46102003)(106466001)(50466002)(229853001)(105586002)(97746001)(19580395003)(54356999)(76176999)(19580405001)(47776003)(50986999)(33646002)(86362001)(2950100001)(110136001)(2351001)(53416004)(92566002)(23676002)(103116003)(87936001)(62966003)(101416001)(71626003); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR02MB416; H:atltwp02.amd.com; FPR:; SPF:None; MLV:sfv; MX:1; A:1; LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM2PR02MB416; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:DM2PR02MB416; BCL:0; PCL:0; RULEID:; SRVR:DM2PR02MB416; X-Forefront-PRVS: 05214FD68E X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2015 16:50:18.8113 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96; Ip=[165.204.84.222]; Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR02MB416 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Use the new lighter weight memory barriers when working with the device descriptors. Signed-off-by: Tom Lendacky --- drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 15 +++++++++------ drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 5 ++++- 2 files changed, 13 insertions(+), 7 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c index 29137c9..e165d06 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c @@ -1068,7 +1068,7 @@ static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) rdesc->desc3 = 0; /* Make sure ownership is written to the descriptor */ - wmb(); + dma_wmb(); } static void xgbe_tx_desc_init(struct xgbe_channel *channel) @@ -1124,12 +1124,12 @@ static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata) * is written to the descriptor(s) before setting the OWN bit * for the descriptor */ - wmb(); + dma_wmb(); XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); /* Make sure ownership is written to the descriptor */ - wmb(); + dma_wmb(); } static void xgbe_rx_desc_init(struct xgbe_channel *channel) @@ -1358,6 +1358,9 @@ static void xgbe_tx_start_xmit(struct xgbe_channel *channel, struct xgbe_prv_data *pdata = channel->pdata; struct xgbe_ring_data *rdata; + /* Make sure everything is written before the register write */ + wmb(); + /* Issue a poll command to Tx DMA by writing address * of next immediate free descriptor */ rdata = XGBE_GET_DESC_DATA(ring, ring->cur); @@ -1565,7 +1568,7 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel) * is written to the descriptor(s) before setting the OWN bit * for the first descriptor */ - wmb(); + dma_wmb(); /* Set OWN bit for the first descriptor */ rdata = XGBE_GET_DESC_DATA(ring, start_index); @@ -1577,7 +1580,7 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel) #endif /* Make sure ownership is written to the descriptor */ - wmb(); + dma_wmb(); ring->cur = cur_index + 1; if (!packet->skb->xmit_more || @@ -1613,7 +1616,7 @@ static int xgbe_dev_read(struct xgbe_channel *channel) return 1; /* Make sure descriptor fields are read after reading the OWN bit */ - rmb(); + dma_rmb(); #ifdef XGMAC_ENABLE_RX_DESC_DUMP xgbe_dump_rx_desc(ring, rdesc, ring->cur); diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c index 885b02b..8635c94 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c @@ -1800,6 +1800,9 @@ static void xgbe_rx_refresh(struct xgbe_channel *channel) ring->dirty++; } + /* Make sure everything is written before the register write */ + wmb(); + /* Update the Rx Tail Pointer Register with address of * the last cleaned entry */ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); @@ -1863,7 +1866,7 @@ static int xgbe_tx_poll(struct xgbe_channel *channel) /* Make sure descriptor fields are read after reading the OWN * bit */ - rmb(); + dma_rmb(); #ifdef XGMAC_ENABLE_TX_DESC_DUMP xgbe_dump_tx_desc(ring, ring->dirty, 1, 0);