From patchwork Tue Oct 7 16:30:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petri Gynther X-Patchwork-Id: 397350 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 07A131400BE for ; Wed, 8 Oct 2014 03:30:31 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754473AbaJGQaF (ORCPT ); Tue, 7 Oct 2014 12:30:05 -0400 Received: from mail-pd0-f202.google.com ([209.85.192.202]:45704 "EHLO mail-pd0-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753873AbaJGQaC (ORCPT ); Tue, 7 Oct 2014 12:30:02 -0400 Received: by mail-pd0-f202.google.com with SMTP id fp1so1120886pdb.3 for ; Tue, 07 Oct 2014 09:30:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:message-id:date; bh=6nLJ6KZe97BUSRip9QmopkUVh6DetSSqdJGE2DoGYXo=; b=AqxFRJxPG1cFrOxo2pIbY18bAKhY7qsuHJEY6XRbpK/NqZvVn3Jn8Z+NVVeUypssHv e5gS5MWTnbAuR8EvABOFw2TdxXv7Yz27pI5YSWLxQvFwuEZcGNkJjOF3WuYj4zFiolIJ 2JLl0xbEDYpWCpO47yUVDqwFY+dz3aAVJKA+0mWnrZogSIn7M1Ez0EieI1BJl0xNLEnD w4KKzSXoBzm7T2E3CiKgSIuDBSjKcWJrMai3W4uMLkZytppwHxVCn4ZlPVf/uyc6/65h FZqbfv4UkFhZ8I4OtPAQ7dPtghlBtjFeXUv6XFehkteNQfFm5uD3b1kF0aL+o8x32bS5 3A6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:message-id:date; bh=6nLJ6KZe97BUSRip9QmopkUVh6DetSSqdJGE2DoGYXo=; b=VIxRsKHm1RgBh/OAMq1VQYw1gTuP6uRUn+P5qT6PXQEQdYTLyZk7KEltX9/T6QOOoI Ue4lYuOvCTgZXX5hd4hGvQsLF5ooWcdnI7VZ7+N+XkjPKuN/5bj454mm0mNtBcFah1HR bSJM1uoADBcLWDpughZ1n4DXARxH+xu363VIILMIreedDyg7X/Whafr3HzeumttvMO6K O+sCLwvMr14p1weOlngXvD5nq4AFGgBO4LG1T+GiFcVzOuCADYWAQ1KuyITyiXySgopD eo3FCIY0AH/ZH6b2QYlrXo5OQjxQNkMQcLfeHQOFg+QF7fYeZkrwurrOUC+Ym8w1k/bE xwwg== X-Gm-Message-State: ALoCoQn4sF6bHSVRyp0CqytLN+idVMbwpZqjEbNR7qPioIajxEtkGmgyV2xsHS19MXT2MXifKRwO X-Received: by 10.68.215.73 with SMTP id og9mr2757725pbc.1.1412699402400; Tue, 07 Oct 2014 09:30:02 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id j25si881655yhb.0.2014.10.07.09.30.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Oct 2014 09:30:02 -0700 (PDT) Received: from puck.mtv.corp.google.com ([172.27.88.166]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id yuVI66dN.1; Tue, 07 Oct 2014 09:30:02 -0700 Received: by puck.mtv.corp.google.com (Postfix, from userid 68020) id 85125100761; Tue, 7 Oct 2014 09:30:01 -0700 (PDT) From: Petri Gynther To: netdev@vger.kernel.org Cc: davem@davemloft.net, f.fainelli@gmail.com Subject: [PATCH v2 net-next] net: bcmgenet: fix Tx ring priority programming Message-Id: <20141007163001.85125100761@puck.mtv.corp.google.com> Date: Tue, 7 Oct 2014 09:30:01 -0700 (PDT) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org GENET MAC has three Tx ring priority registers: - GENET_x_TDMA_PRIORITY0 for queues 0-5 - GENET_x_TDMA_PRIORITY1 for queues 6-11 - GENET_x_TDMA_PRIORITY2 for queues 12-16 Fix bcmgenet_init_multiq() to program them correctly. Signed-off-by: Petri Gynther Acked-by: Florian Fainelli --- drivers/net/ethernet/broadcom/genet/bcmgenet.c | 42 +++++++++++++++----------- drivers/net/ethernet/broadcom/genet/bcmgenet.h | 2 ++ 2 files changed, 27 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index e0a6238..fff2634 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -191,8 +191,9 @@ enum dma_reg { DMA_STATUS, DMA_SCB_BURST_SIZE, DMA_ARB_CTRL, - DMA_PRIORITY, - DMA_RING_PRIORITY, + DMA_PRIORITY_0, + DMA_PRIORITY_1, + DMA_PRIORITY_2, }; static const u8 bcmgenet_dma_regs_v3plus[] = { @@ -201,8 +202,9 @@ static const u8 bcmgenet_dma_regs_v3plus[] = { [DMA_STATUS] = 0x08, [DMA_SCB_BURST_SIZE] = 0x0C, [DMA_ARB_CTRL] = 0x2C, - [DMA_PRIORITY] = 0x30, - [DMA_RING_PRIORITY] = 0x38, + [DMA_PRIORITY_0] = 0x30, + [DMA_PRIORITY_1] = 0x34, + [DMA_PRIORITY_2] = 0x38, }; static const u8 bcmgenet_dma_regs_v2[] = { @@ -211,8 +213,9 @@ static const u8 bcmgenet_dma_regs_v2[] = { [DMA_STATUS] = 0x08, [DMA_SCB_BURST_SIZE] = 0x0C, [DMA_ARB_CTRL] = 0x30, - [DMA_PRIORITY] = 0x34, - [DMA_RING_PRIORITY] = 0x3C, + [DMA_PRIORITY_0] = 0x34, + [DMA_PRIORITY_1] = 0x38, + [DMA_PRIORITY_2] = 0x3C, }; static const u8 bcmgenet_dma_regs_v1[] = { @@ -220,8 +223,9 @@ static const u8 bcmgenet_dma_regs_v1[] = { [DMA_STATUS] = 0x04, [DMA_SCB_BURST_SIZE] = 0x0C, [DMA_ARB_CTRL] = 0x30, - [DMA_PRIORITY] = 0x34, - [DMA_RING_PRIORITY] = 0x3C, + [DMA_PRIORITY_0] = 0x34, + [DMA_PRIORITY_1] = 0x38, + [DMA_PRIORITY_2] = 0x3C, }; /* Set at runtime once bcmgenet version is known */ @@ -1696,7 +1700,8 @@ static void bcmgenet_init_multiq(struct net_device *dev) { struct bcmgenet_priv *priv = netdev_priv(dev); unsigned int i, dma_enable; - u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0; + u32 reg, dma_ctrl, ring_cfg = 0; + u32 dma_priority[3] = {0, 0, 0}; if (!netif_is_multiqueue(dev)) { netdev_warn(dev, "called with non multi queue aware HW\n"); @@ -1721,22 +1726,25 @@ static void bcmgenet_init_multiq(struct net_device *dev) /* Configure ring as descriptor ring and setup priority */ ring_cfg |= 1 << i; - dma_priority |= ((GENET_Q0_PRIORITY + i) << - (GENET_MAX_MQ_CNT + 1) * i); dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT); + + dma_priority[DMA_PRIO_REG_INDEX(i)] |= + ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); } + /* Set ring 16 priority and program the hardware registers */ + dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= + ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << + DMA_PRIO_REG_SHIFT(DESC_INDEX)); + bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); + bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); + bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); + /* Enable rings */ reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG); reg |= ring_cfg; bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG); - /* Use configured rings priority and set ring #16 priority */ - reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY); - reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20); - reg |= dma_priority; - bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY); - /* Configure ring as descriptor ring and re-enable DMA if enabled */ reg = bcmgenet_tdma_readl(priv, DMA_CTRL); reg |= dma_ctrl; diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.h b/drivers/net/ethernet/broadcom/genet/bcmgenet.h index 321b1db..dbf524e 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.h +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h @@ -401,6 +401,8 @@ struct bcmgenet_mib_counters { #define DMA_ARBITER_MODE_MASK 0x03 #define DMA_RING_BUF_PRIORITY_MASK 0x1F #define DMA_RING_BUF_PRIORITY_SHIFT 5 +#define DMA_PRIO_REG_INDEX(q) ((q) / 6) +#define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) #define DMA_RATE_ADJ_MASK 0xFF /* Tx/Rx Dma Descriptor common bits*/