From patchwork Tue Aug 27 16:13:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 270153 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E1B2E2C00DB for ; Wed, 28 Aug 2013 02:14:08 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753435Ab3H0QOE (ORCPT ); Tue, 27 Aug 2013 12:14:04 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:51982 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753294Ab3H0QOC (ORCPT ); Tue, 27 Aug 2013 12:14:02 -0400 Received: by mail-pd0-f170.google.com with SMTP id x10so5107493pdj.1 for ; Tue, 27 Aug 2013 09:14:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=5u8JEyMnkAzl1IRoMMST7KiaweeYeQNcvfmxDobjuIM=; b=AGEtOD6P6+A8D1x1sZQ+LIW3ADWCaT0SwYIbhfnA6mry9zTjzD4Prs64H4enkQ17jn dD85MoP23sqktaqNIZF1bJvEMO8Ku9dsqdYRMQh1jzis22pxadXcQEgE7pHWUWEEPQyx qvktLvC6bdPPgN4hvqm6MEePPHalq+YvJdr4Mw7BOCC54qtzAIUedstS6YwFxp2lLa81 QbAd4eQ1doQaOCLAFF9+HpoY1hj6pFVYb0YKsxO7HoBbZ35Jg9UhAYYl40b7An34yrdx xzlYsmAZZTJCQN3Yq3pWD10f2akpGlOIuKh/DA52mKRYJFSmY8TiZC+isQj9qMM0nDrH XnYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=5u8JEyMnkAzl1IRoMMST7KiaweeYeQNcvfmxDobjuIM=; b=XZL6/C77sJOva6KnQRIYbh4O695c1HPB5lzr8Wya5pE0Rslq24hYstcI/lDlzUiTb4 acUH5Kn3cDXOt9K49kThfjgexZdxalBBfmSoR87xWSO/sC5RtpRJHA7fWB0WGbfB1Qft 2UFHT25veNMvUHP7wAf0nGgRdq2hGnJD7ME6S9l0cXxRZhbAZbmTge27DqciIMgHAMra iGHFiT2Z07cC2cWtOf2YV9mpygxOeEdnwbE3Lh9fSSeLwqo9gzIXd4KhZl/C1hPgJw56 wXWl6B9N+ZXDhI9ztN2TDuyMIo9U5RRS9OmNJbxM20jN7YoDQSsTrtcX1YRLSkjyuUdv 7Bog== X-Gm-Message-State: ALoCoQlQUyn2kmOmabHfad0JMTq0zxYOaBJd+ObpZ9LYliJh1V0WD5efN5mSAWeloSmkRSMcReYi1RaHlBIDLS90wE+/51en6HwmhqHuLF2Ncr3mHLClVn0odGuSOBHxJzzf92c7S+dl489oaQpa2tDzSFDuF3VETfw3R4Bp1pEZzXGkhml6tm0L1hRyhfvLHOQeGcZctUNsuq++cb5tJoy4zY8rBzBppA== X-Received: by 10.66.231.42 with SMTP id td10mr10063721pac.144.1377620041534; Tue, 27 Aug 2013 09:14:01 -0700 (PDT) Received: from google.com ([172.19.241.6]) by mx.google.com with ESMTPSA id br3sm25512078pbd.31.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 27 Aug 2013 09:14:00 -0700 (PDT) Date: Tue, 27 Aug 2013 10:13:57 -0600 From: Bjorn Helgaas To: Yuval Mintz Cc: "jacob.e.keller@intel.com" , "linux-pci@vger.kernel.org" , "netdev@vger.kernel.org" , Jiang Liu Subject: Re: pcie_get_minimum_link returns 0 width Message-ID: <20130827161357.GA21180@google.com> References: <20130825100157.GA16500@lb-tlvb-yuvalmin.il.broadcom.com> <979A8436335E3744ADCD3A9F2A2B68A52AD136BE@SJEXCHMB10.corp.ad.broadcom.com> <979A8436335E3744ADCD3A9F2A2B68A52AD13D0C@SJEXCHMB10.corp.ad.broadcom.com> <979A8436335E3744ADCD3A9F2A2B68A52AD13FB9@SJEXCHMB10.corp.ad.broadcom.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Tue, Aug 27, 2013 at 07:57:20AM -0600, Bjorn Helgaas wrote: > [+cc Jiang] > > On Tue, Aug 27, 2013 at 1:40 AM, Yuval Mintz wrote: > >> On Mon, Aug 26, 2013 at 5:36 PM, Yuval Mintz > >> wrote: > >> >> > Hi, > >> >> > > >> >> > I tried adding support for the newly added 'pcie_get_minimum_link' into > >> >> the > >> >> > bnx2x driver, but found out the some of my devices started showing > >> width > >> >> x0. > >> >> > > >> >> > By adding debug prints, I've found out there were devices up the chain > >> that > >> >> > Showed 0 when their PCI_EXP_LNKSTA was read by said function. > >> >> > However, when I tried looking via lspci the output claimed the width was > >> >> x4. > >> Looking at its implementation, one obvious difference is that > >> pcie_get_minimum_link() traverses up the hierarchy and keeps track of > >> the minimum values it finds. lspci, on the other hand, just reads > >> PCI_EXP_LNKSTA from a single device and decodes it. > >> > >> You said lspci reports x4 for every device from the Root Port all the > >> way down to your NIC, so I would think the minimum from > >> pcie_get_minimum_link() would be x4. But apparently it's not. Maybe > >> there's a bug in it. Can you post the complete "lspci -vv" output > >> along with your debug patch and output? > >> > >> Bjorn > > > > Here's the patch: > > --- > > drivers/pci/pci.c | 8 +++++++- > > 1 files changed, 7 insertions(+), 1 deletions(-) > > > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > > index c71e78c..72cb87b 100644 > > --- a/drivers/pci/pci.c > > +++ b/drivers/pci/pci.c > > @@ -3601,13 +3601,19 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, > > enum pcie_link_width next_width; > > > > ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); > > - if (ret) > > + if (ret) { > > + printk(KERN_ERR "Failed to Read LNKSTA\n"); > > return ret; > > + } > > > > next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; > > next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> > > PCI_EXP_LNKSTA_NLW_SHIFT; > > > > + printk(KERN_ERR "LnkSta %04x [%04x:%02x.%02x]\n", > > + lnksta, dev->bus->number, PCI_SLOT(dev->devfn), > > + PCI_FUNC(dev->devfn)); > > I think pcie_cap_has_lnkctl() is incorrect: it currently thinks only > Root Ports, Endpoints, and Legacy Endpoints have link registers. But > I think switch ports (Upstream Ports and Downstream Ports) also have > link registers (PCIe spec r3.0, sec 7.8). Jiang? Yuval, can you try the patch below? PCI: Allow access to link-related registers for switch and bridge ports From: Bjorn Helgaas Every PCIe device has a link, except Root Complex Integrated Endpoints and Root Complex Event Collectors. Previously we didn't give access to PCIe capability link-related registers for Upstream Ports, Downstream Ports, and bridges, so attempts to read PCI_EXP_LNKCTL returned zero. See PCIe spec r3.0, sec 7.8 and 1.3.2.3. Reported-by: Yuval Mintz Signed-off-by: Bjorn Helgaas --- drivers/pci/access.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/access.c b/drivers/pci/access.c index 1cc2366..46dd5ad 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -485,9 +485,8 @@ static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev) int type = pci_pcie_type(dev); return pcie_cap_version(dev) > 1 || - type == PCI_EXP_TYPE_ROOT_PORT || - type == PCI_EXP_TYPE_ENDPOINT || - type == PCI_EXP_TYPE_LEG_END; + !(type == PCI_EXP_TYPE_RC_END || + type == PCI_EXP_TYPE_RC_EC); } static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)