From patchwork Thu Sep 10 02:01:30 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Vorontsov X-Patchwork-Id: 33264 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id D243DB7CF2 for ; Thu, 10 Sep 2009 12:01:38 +1000 (EST) Received: by ozlabs.org (Postfix) id C044FDDD0C; Thu, 10 Sep 2009 12:01:38 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by ozlabs.org (Postfix) with ESMTP id 6AA33DDD01 for ; Thu, 10 Sep 2009 12:01:38 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754853AbZIJCB3 (ORCPT ); Wed, 9 Sep 2009 22:01:29 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754077AbZIJCB3 (ORCPT ); Wed, 9 Sep 2009 22:01:29 -0400 Received: from ru.mvista.com ([213.79.90.228]:26211 "EHLO buildserver.ru.mvista.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751530AbZIJCB2 (ORCPT ); Wed, 9 Sep 2009 22:01:28 -0400 Received: from localhost (unknown [10.150.0.9]) by buildserver.ru.mvista.com (Postfix) with ESMTP id CAF218824; Thu, 10 Sep 2009 07:01:30 +0500 (SAMST) Date: Thu, 10 Sep 2009 06:01:30 +0400 From: Anton Vorontsov To: David Miller Cc: Andy Fleming , Timur Tabi , Li Yang , Kumar Gala , netdev@vger.kernel.org, linuxppc-dev@ozlabs.org Subject: [PATCH 1/3] phy/marvell: Make non-aneg speed/duplex forcing work for 88E1111 PHYs Message-ID: <20090910020130.GA31083@oksana.dev.rtsoft.ru> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org According to specs, when auto-negotiation is disabled, Marvell PHYs need a software reset after changing speed/duplex forcing bits. Otherwise, the modified bits have no effect. Signed-off-by: Anton Vorontsov --- drivers/net/phy/marvell.c | 21 ++++++++++++++++++++- 1 files changed, 20 insertions(+), 1 deletions(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index dd6f54d..6f69b9b 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -155,8 +155,27 @@ static int marvell_config_aneg(struct phy_device *phydev) return err; err = genphy_config_aneg(phydev); + if (err < 0) + return err; - return err; + if (phydev->autoneg != AUTONEG_ENABLE) { + int bmcr; + + /* + * A write to speed/duplex bits (that is performed by + * genphy_config_aneg() call above) must be followed by + * a software reset. Otherwise, the write has no effect. + */ + bmcr = phy_read(phydev, MII_BMCR); + if (bmcr < 0) + return bmcr; + + err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); + if (err < 0) + return err; + } + + return 0; } static int m88e1121_config_aneg(struct phy_device *phydev)