From patchwork Tue Apr 2 12:56:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 1074395 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="QoxDvO9+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44YTjk6fkLz9sP7 for ; Tue, 2 Apr 2019 23:56:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729482AbfDBM4V (ORCPT ); Tue, 2 Apr 2019 08:56:21 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:9779 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725920AbfDBM4V (ORCPT ); Tue, 2 Apr 2019 08:56:21 -0400 X-IronPort-AV: E=Sophos;i="5.60,300,1549954800"; d="scan'208";a="29305566" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 02 Apr 2019 05:56:20 -0700 Received: from NAM03-CO1-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.76.38) with Microsoft SMTP Server (TLS) id 14.3.352.0; Tue, 2 Apr 2019 05:56:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector1-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=I7uzM7XVbU/TWlqewEl/Ab72vAyQTu7V7od1m2XaJno=; b=QoxDvO9+vKGNgClZILY6V5ceCnFncxRtn0FdPbbryKcT4K08Yu8YnpXvVB6JDtanGF9gMcD9WEj+J0cvsWvF+I0cdfLAdz6j4tgOhMU7OdWpIg6LiLQyLJysNk6iBr+iv8nf+UK/eMsS9Yfah5Sc2d6zOlWa7kiAIsnSdKPxmjs= Received: from DM5PR11MB1242.namprd11.prod.outlook.com (10.168.108.8) by DM5PR11MB0043.namprd11.prod.outlook.com (10.164.155.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.16; Tue, 2 Apr 2019 12:56:18 +0000 Received: from DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::e8b6:2ae9:9b9c:2ca8]) by DM5PR11MB1242.namprd11.prod.outlook.com ([fe80::e8b6:2ae9:9b9c:2ca8%3]) with mapi id 15.20.1750.014; Tue, 2 Apr 2019 12:56:18 +0000 From: To: , , , , , CC: , Subject: [PATCH RESEND] can: m_can: implement errata "Needless activation of MRAF irq" Thread-Topic: [PATCH RESEND] can: m_can: implement errata "Needless activation of MRAF irq" Thread-Index: AQHU6VN26GhpB23BUk+qk1eaBs8P4g== Date: Tue, 2 Apr 2019 12:56:18 +0000 Message-ID: <1554209445-19879-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: ro-RO, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VE1PR08CA0020.eurprd08.prod.outlook.com (2603:10a6:803:104::33) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Eugen.Hristev@microchip.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d7774154-0e05-4af3-7635-08d6b76a98f5 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:DM5PR11MB0043; x-ms-traffictypediagnostic: DM5PR11MB0043: x-ms-exchange-purlcount: 1 x-microsoft-antispam-prvs: x-forefront-prvs: 0995196AA2 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(136003)(396003)(346002)(39860400002)(376002)(199004)(189003)(6486002)(36756003)(478600001)(4326008)(26005)(6506007)(99286004)(14454004)(68736007)(386003)(186003)(6306002)(71190400001)(486006)(6512007)(966005)(102836004)(2501003)(110136005)(5660300002)(72206003)(66066001)(86362001)(97736004)(53936002)(316002)(54906003)(2906002)(105586002)(106356001)(81166006)(25786009)(3846002)(8936002)(81156014)(2201001)(107886003)(6436002)(14444005)(476003)(6116002)(305945005)(2616005)(7736002)(71200400001)(8676002)(52116002)(50226002)(256004); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB0043; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: bFUfWRqKNPiP5W+UNlVLPDHXR167KjvXAMWMPuUdD04l+OO7ZQMBFtKznnDs65PNY5mn5vqBq+G8JnGl0PDNAD+KJO6wZ0VnYxFFJ0F4BzMBaXdfFSknzwUh/xYxVs4IEaD5jo5+9oJ/EnGoCKOAkUbzBKKBSUIJQe0IZcX0HfTEJFGoRJN6PPccZ8u6LfdafV1FGaL796ILK/LfiSD2Dr8BhtYruAs8eA3Bpmyvjd+VC6alw9JaQ/j4sdABOcMQRvo1r/sPTDUOwsn3nTp0cx0P0TwFm8j7pk+fllyx5lv8srHZ4Om/XWBkgURMtD0vpa1zuWhnFU3k7Wq9Sj1giKtg/hGqPr+ttbhqVlHmHhRB4z8scRC8jbWE5tcWSBXaESoKLJFN2mtS8o6D8SrKa02bfIVwRSPDz8Vsi4kHPpw= Content-ID: <91BD978EDD9B304FB76BE35694252BD2@namprd11.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: d7774154-0e05-4af3-7635-08d6b76a98f5 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2019 12:56:18.3476 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0043 X-OriginatorOrg: microchip.com Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Eugen Hristev During frame reception while the MCAN is in Error Passive state and the Receive Error Counter has thevalue MCAN_ECR.REC = 127, it may happen that MCAN_IR.MRAF is set although there was no Message RAM access failure. If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated. Work around: The Message RAM Access Failure interrupt routine needs to check whether MCAN_ECR.RP = '1' and MCAN_ECR.REC = '127'. In this case, reset MCAN_IR.MRAF. No further action is required. This affects versions older than 3.2.0 Errata explained on Sama5d2 SoC which includes this hardware block: http://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Family-Silicon-Errata-and-Data-Sheet-Clarification-DS80000803B.pdf chapter 6.2 Reproducibility: If 2 devices with m_can are connected back to back, configuring different bitrate on them will lead to interrupt storm on the receiving side, with error "Message RAM access failure occurred". Another way is to have a bad hardware connection. Bad wire connection can lead to this issue as well. This patch fixes the issue according to provided workaround. Signed-off-by: Eugen Hristev Reviewed-by: Ludovic Desroches --- drivers/net/can/m_can/m_can.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 9b44940..deb274a 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -822,6 +822,27 @@ static int m_can_poll(struct napi_struct *napi, int quota) if (!irqstatus) goto end; + /* Errata workaround for issue "Needless activation of MRAF irq" + * During frame reception while the MCAN is in Error Passive state + * and the Receive Error Counter has the value MCAN_ECR.REC = 127, + * it may happen that MCAN_IR.MRAF is set although there was no + * Message RAM access failure. + * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated + * The Message RAM Access Failure interrupt routine needs to check + * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. + * In this case, reset MCAN_IR.MRAF. No further action is required. + */ + if ((priv->version <= 31) && (irqstatus & IR_MRAF) && + (m_can_read(priv, M_CAN_ECR) & ECR_RP)) { + struct can_berr_counter bec; + + __m_can_get_berr_counter(dev, &bec); + if (bec.rxerr == 127) { + m_can_write(priv, M_CAN_IR, IR_MRAF); + irqstatus &= ~IR_MRAF; + } + } + psr = m_can_read(priv, M_CAN_PSR); if (irqstatus & IR_ERR_STATE) work_done += m_can_handle_state_errors(dev, psr);