Message ID | 1510127543-34158-2-git-send-email-lipeng321@huawei.com |
---|---|
State | Accepted, archived |
Delegated to: | David Miller |
Headers | show |
Series | net: hns3: Bug fixes & Code improvements in HNS3 driver | expand |
On Wed, Nov 08, 2017 at 03:52:22PM +0800, Lipeng wrote: > From: Fuyun Liang <liangfuyun1@huawei.com> > > Driver gets phy address from NCL_config file and uses the phy address > to initialize phydev. There are 5 bits for phy address. And C22 phy > address has 5 bits. So 0-31 are all valid address for phy. If there > is no phy, it will crash. Because driver always get a valid phy address. Hi Lipeng Any plans for C45? The PHY address is still 5 bits, but do you need to get the device type from your configuration file? Andrew
Hi Andrew, > -----Original Message----- > From: Andrew Lunn [mailto:andrew@lunn.ch] > Sent: Wednesday, November 08, 2017 2:31 PM > To: lipeng (Y) > Cc: davem@davemloft.net; netdev@vger.kernel.org; linux- > kernel@vger.kernel.org; Linuxarm; Zhuangyuzeng (Yisen); Salil Mehta > Subject: Re: [PATCH net-next 1/2] net: hns3: fix a bug when getting phy > address from NCL_config file > > On Wed, Nov 08, 2017 at 03:52:22PM +0800, Lipeng wrote: > > From: Fuyun Liang <liangfuyun1@huawei.com> > > > > Driver gets phy address from NCL_config file and uses the phy address > > to initialize phydev. There are 5 bits for phy address. And C22 phy > > address has 5 bits. So 0-31 are all valid address for phy. If there > > is no phy, it will crash. Because driver always get a valid phy > address. > > Hi Lipeng > > Any plans for C45? Still remember the kernel change required to support C45 discussed with you some time back :). Will try to push that change as soon as possible. And yes, we would be pushing the support of the C45 for HNS3 driver as well after that. Thanks Salil
On 2017/11/8 22:30, Andrew Lunn wrote: > On Wed, Nov 08, 2017 at 03:52:22PM +0800, Lipeng wrote: >> From: Fuyun Liang <liangfuyun1@huawei.com> >> >> Driver gets phy address from NCL_config file and uses the phy address >> to initialize phydev. There are 5 bits for phy address. And C22 phy >> address has 5 bits. So 0-31 are all valid address for phy. If there >> is no phy, it will crash. Because driver always get a valid phy address. > Hi Lipeng > > Any plans for C45? The PHY address is still 5 bits, but do you need to > get the device type from your configuration file? > > Andrew Hi Andrew C45 support is in Plan, now only support C22. This bugfix patch is valid for C22 and C45. As plan , will get the device type(NULL, C22, C45) from configuration file after support C45. Do you think we must do it now? or can add it along with C45 support? Lipeng > . >
On Thu, Nov 09, 2017 at 10:02:37AM +0800, lipeng (Y) wrote: > > > On 2017/11/8 22:30, Andrew Lunn wrote: > >On Wed, Nov 08, 2017 at 03:52:22PM +0800, Lipeng wrote: > >>From: Fuyun Liang <liangfuyun1@huawei.com> > >> > >>Driver gets phy address from NCL_config file and uses the phy address > >>to initialize phydev. There are 5 bits for phy address. And C22 phy > >>address has 5 bits. So 0-31 are all valid address for phy. If there > >>is no phy, it will crash. Because driver always get a valid phy address. > >Hi Lipeng > > > >Any plans for C45? The PHY address is still 5 bits, but do you need to > >get the device type from your configuration file? > > > > Andrew > Hi Andrew > > C45 support is in Plan, now only support C22. > This bugfix patch is valid for C22 and C45. Great. That is all i wanted to know. Thanks Andrew
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h index 844c83e..ce5ed88 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h @@ -390,7 +390,7 @@ struct hclge_pf_res_cmd { #define HCLGE_CFG_TQP_DESC_N_S 16 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) #define HCLGE_CFG_PHY_ADDR_S 0 -#define HCLGE_CFG_PHY_ADDR_M GENMASK(4, 0) +#define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) #define HCLGE_CFG_MEDIA_TP_S 8 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) #define HCLGE_CFG_RX_BUF_LEN_S 16