From patchwork Tue Aug 29 20:35:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 807295 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="uT2AllI+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xhgXN3CmHz9s9Y for ; Wed, 30 Aug 2017 06:41:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751660AbdH2UlV (ORCPT ); Tue, 29 Aug 2017 16:41:21 -0400 Received: from mail-qt0-f195.google.com ([209.85.216.195]:38868 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751558AbdH2UlS (ORCPT ); Tue, 29 Aug 2017 16:41:18 -0400 Received: by mail-qt0-f195.google.com with SMTP id d15so3751713qta.5 for ; Tue, 29 Aug 2017 13:41:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wdYHDGbFKVHeTJrAUUS/W8EgmsxN6o+2p79L7/vCJyw=; b=uT2AllI+Mde4/OqkYdmzJhgH5Fgi+ysqTY4uuTq22NFn4ZcooH1N7yw5HvFUOpJHzC OEEifUFCBL1Xe7TmOWZLkfdirKqASO43uqZE652HmKB0oMXHsIV0Nxgyxlp4mKGzigPK SxV6hSwW+RbQng9b7hrFBaU3WK0rSOzRvoKd4YfkMVKGJN3bx58VXLTjLqurMmxaQWIh LGiQi616+ADWd90/MWG4qxzqJxiYSDWNjywmTZ3SXvq3TVMfSHaktlVtE1Evak/2KIlt yqKcHd4YgObsnyaJaDPV2Tmav0bQ09mfTYJW/U2XB1nSKK3Zsx8ezKkin5TOcQBqpmvA yUqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wdYHDGbFKVHeTJrAUUS/W8EgmsxN6o+2p79L7/vCJyw=; b=BKByStZATT7qPFcF1rKgkNANv8zvgcWpIiWimLK4a47ibwDwPu//KuODMlGZJI6nbe gxdHm229ALH2F/7JzpVARQRCpSyDNE7+SuEp70t1FZ3O/ePC6UhWbDo4IKJlriH41UPZ 1cF7QSYT3mpq2S6sIV+kgJZFweK1U1uQe1FkIB8Er8ulSLvtC4/IOG8ZsJwg06x4YFHs u3RhQpqu4OtldyVM6uTCsXNyyRQbz1j19h9xnZxQ+OT9dyXuSHD37qnwkj2jj7CVMWSd cYdm/R4n4Q7qkfWM3/O60BIJLMsBRyAOjO9EaVaxx53QYq7l9j/ZEiE8eHNusfbWTw8f PVOw== X-Gm-Message-State: AHYfb5jcuVjnlztl0Lk8yTXckQJQxpuQrVU59NB3u2g7nYMURzGHJ8jY OC4cD/KkA1h/eNEB+L8= X-Received: by 10.200.15.87 with SMTP id l23mr7352479qtk.292.1504039277938; Tue, 29 Aug 2017 13:41:17 -0700 (PDT) Received: from stb-bld-04.irv.broadcom.com ([192.19.255.250]) by smtp.gmail.com with ESMTPSA id u17sm2645446qtc.43.2017.08.29.13.41.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 13:41:16 -0700 (PDT) From: Florian Fainelli To: netdev@vger.kernel.org Cc: davem@davemloft.net, opendmb@gmail.com, andrew@lunn.ch, vivien.didelot@savoirfairelinux.com, Florian Fainelli Subject: [PATCH net-next v2 2/4] net: dsa: bcm_sf2: Use correct I/O accessors Date: Tue, 29 Aug 2017 13:35:16 -0700 Message-Id: <1504038918-49254-3-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1504038918-49254-1-git-send-email-f.fainelli@gmail.com> References: <1504038918-49254-1-git-send-email-f.fainelli@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The Starfigther 2 driver currently uses __raw_{read,write}l which means native I/O endian. This works correctly for an ARM LE kernel (default) but fails miserably on an ARM BE (BE8) kernel where registers are kept little endian, so replace uses with {read,write}l_relaxed here which is what we want because this is all performance sensitive code. Signed-off-by: Florian Fainelli --- drivers/net/dsa/bcm_sf2.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/bcm_sf2.h b/drivers/net/dsa/bcm_sf2.h index 7d3030e04f11..d9c96b281fc0 100644 --- a/drivers/net/dsa/bcm_sf2.h +++ b/drivers/net/dsa/bcm_sf2.h @@ -130,12 +130,12 @@ static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off) #define SF2_IO_MACRO(name) \ static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \ { \ - return __raw_readl(priv->name + off); \ + return readl_relaxed(priv->name + off); \ } \ static inline void name##_writel(struct bcm_sf2_priv *priv, \ u32 val, u32 off) \ { \ - __raw_writel(val, priv->name + off); \ + writel_relaxed(val, priv->name + off); \ } \ /* Accesses to 64-bits register requires us to latch the hi/lo pairs @@ -179,23 +179,23 @@ static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off) static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off) { u32 tmp = bcm_sf2_mangle_addr(priv, off); - return __raw_readl(priv->core + tmp); + return readl_relaxed(priv->core + tmp); } static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) { u32 tmp = bcm_sf2_mangle_addr(priv, off); - __raw_writel(val, priv->core + tmp); + writel_relaxed(val, priv->core + tmp); } static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off) { - return __raw_readl(priv->reg + priv->reg_offsets[off]); + return readl_relaxed(priv->reg + priv->reg_offsets[off]); } static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off) { - __raw_writel(val, priv->reg + priv->reg_offsets[off]); + writel_relaxed(val, priv->reg + priv->reg_offsets[off]); } SF2_IO64_MACRO(core);