From patchwork Thu Feb 16 15:22:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiri Pirko X-Patchwork-Id: 728752 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vPKfS2wNhz9s8T for ; Fri, 17 Feb 2017 02:22:56 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=resnulli-us.20150623.gappssmtp.com header.i=@resnulli-us.20150623.gappssmtp.com header.b="1riW6+IM"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932438AbdBPPWx (ORCPT ); Thu, 16 Feb 2017 10:22:53 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:33110 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932423AbdBPPWu (ORCPT ); Thu, 16 Feb 2017 10:22:50 -0500 Received: by mail-wm0-f66.google.com with SMTP id v77so3650659wmv.0 for ; Thu, 16 Feb 2017 07:22:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=resnulli-us.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ygDMP2aQbLiMujlrKuDXNXhLHbzTaP3XoBywNGgWrYc=; b=1riW6+IMkGORpIQ8DkA+twTVFblf0D6hwk5vxJlxLRqiEFUZkRxY9o5eAz15q1TboV qwxb9CsMTLBFQcgwTezTQI3f20pHZ1Fr71bxNgYuYvHXsO+tC2CAizXzZprOcG1v2aNI D3VgLvbS6i2+VJuCpg1P+MJojLt1Xf6QbtGi7XQTMpq6PKU/W/OGq/n2D/3wuhh6HRCr Fjb4h3OznRtNVs1bhjLNqBoataP6S7hQ8CYRwxxyIXyiTFfaiUPz/pC+xwGoNMHC27gr IpVtRFMmFYQrwQuKPFDbSHLe3hvg5Fdwgf/xWHN9X/YiMV+mFR9OICbT5RH+m7JiLUFg LT9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ygDMP2aQbLiMujlrKuDXNXhLHbzTaP3XoBywNGgWrYc=; b=qMZ9RhHM06ktEAh/yxIm3Bh3Thvf/NMkASL+pmwGYNMnOUz2pjXY05aZhnsTDs9G1b w9kuELt8lfvklLeaXSUqVY7CIlFF42HEGIlmgQOXUkXfkKd7S7vnzTms3cr601ayzYOn /fmg8leE2Z4ZFbcdkhZ7Lyd30XXcPBtt3aTTO+N+kNzXgDhy+W5kTPLZAOIvdp5k89wl 00PXT4wDq3Ea1AvLyIc900ln9NebZ7TK6LYhdKw2PkLs3b8jNaMr2sJiV/NaLlltgOYO zc4Ms/M93W5AzyrJ2Ln4/6LOD94x8N8kdKWt7x+HMIm8R1jpIamQDRnuUlQsICpEtiI8 6L9g== X-Gm-Message-State: AMke39l9BtgUOFRjvGJE2TNeq8qU1Z4Oh5f0caintoxt61rotQ9zZ8Ue8pMwC9xTcUNioA== X-Received: by 10.28.5.72 with SMTP id 69mr2845941wmf.6.1487258569248; Thu, 16 Feb 2017 07:22:49 -0800 (PST) Received: from localhost (ip-78-45-162-92.net.upcbroadband.cz. [78.45.162.92]) by smtp.gmail.com with ESMTPSA id r195sm655128wme.25.2017.02.16.07.22.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Feb 2017 07:22:48 -0800 (PST) From: Jiri Pirko To: netdev@vger.kernel.org Cc: davem@davemloft.net, arkadis@mellanox.com, idosch@mellanox.com, mlxsw@mellanox.com, jhs@mojatatu.com, ivecera@redhat.com, roopa@cumulusnetworks.com, f.fainelli@gmail.com, vivien.didelot@savoirfairelinux.com, john.fastabend@gmail.com, andrew@lunn.ch Subject: [patch net-next RFC 3/8] mlxsw: reg: Add counter fields to RITR register Date: Thu, 16 Feb 2017 16:22:39 +0100 Message-Id: <1487258564-3775-4-git-send-email-jiri@resnulli.us> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487258564-3775-1-git-send-email-jiri@resnulli.us> References: <1487258564-3775-1-git-send-email-jiri@resnulli.us> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Arkadi Sharshevsky Update RITR for counter support. This allows adding counters for ASIC's router ports. Signed-off-by: Arkadi Sharshevsky Signed-off-by: Jiri Pirko --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 54 +++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 0899e2d..6066689 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -4125,6 +4125,60 @@ MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); */ MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); +/* Shared between ingress/egress */ +enum mlxsw_reg_ritr_counter_set_type { + /* No Count. */ + MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, + /* Basic. Used for router interfaces, counting the following: + * - Error and Discard counters. + * - Unicast, Multicast and Broadcast counters. Sharing the + * same set of counters for the different type of traffic + * (IPv4, IPv6 and mpls). + */ + MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, +}; + +/* reg_ritr_ingress_counter_index + * Counter Index for flow counter. + * Access: RW + */ +MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); + +/* reg_ritr_ingress_counter_set_type + * Igress Counter Set Type for router interface counter. + * Access: RW + */ +MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); + +/* reg_ritr_egress_counter_index + * Counter Index for flow counter. + * Access: RW + */ +MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); + +/* reg_ritr_egress_counter_set_type + * Egress Counter Set Type for router interface counter. + * Access: RW + */ +MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); + +static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, + bool enable, bool egress) +{ + enum mlxsw_reg_ritr_counter_set_type set_type; + + if (enable) + set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; + else + set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; + mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); + + if (egress) + mlxsw_reg_ritr_egress_counter_index_set(payload, index); + else + mlxsw_reg_ritr_ingress_counter_index_set(payload, index); +} + static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) { MLXSW_REG_ZERO(ritr, payload);