From patchwork Tue Apr 26 21:24:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joachim Eastwood X-Patchwork-Id: 615307 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qvbjd3j7bz9t5g for ; Wed, 27 Apr 2016 07:25:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=0CkNWSX0; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753223AbcDZVZj (ORCPT ); Tue, 26 Apr 2016 17:25:39 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:35948 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752477AbcDZVZd (ORCPT ); Tue, 26 Apr 2016 17:25:33 -0400 Received: by mail-lf0-f65.google.com with SMTP id y84so4293639lfc.3 for ; Tue, 26 Apr 2016 14:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L5bY3FMjbkr+S2ZbHJbrygFLsAHOdE+4J0E0UgJvkXs=; b=0CkNWSX0x5f+ODGAHwvRlKPFA1FIKi3NNCaAQwCRK2IBAdwf6LUVrifnzFjityQTNc tATn6eNhAB8SS54AYpwJnhZVi896ghhOrBaOP8JmzirFL3wWaGsubnx5ZaV/KUNp2Dr0 p0o/wtxKQwvX/aELEoMyYqgzoWB8mxf0xiIBZrDmOGtV7ydxKrLuYHTicrydw7ZPfGrk Jrq9qvqemUSZLWSPBx5g5N6bCxMrP9ADGPc4kZfmS6AVi/fYXYM3XD6kWEOv8Ouqj/+N CoZs+8Y1aaCHzubZpVManIwc0zoksSfDCmsS488JiFjcQlYu1INgev8s4LFSGbOtUs+R 2IUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L5bY3FMjbkr+S2ZbHJbrygFLsAHOdE+4J0E0UgJvkXs=; b=FhqV4fE8HrUFx0dZF1gFKag4GZ2gRLe7uVPrqobuqFyYS4fOlndEDQy2x4/brt+DdF yW17b8QU7xUeNAqqWXUeiP61hdgLRzr8NCr6WQ9woGqVD0UgQh40anW5RNifk4ts5oV3 PAXBQwXEDhb1rcrVje1hQf7li67e3s3WGg3nA1sqeXM4KHTLEssA0hiN3WTgfeeC0GHS l2Y+LPXlKcJm34/Dix7P6D/gmpVfeojFoxg0WeYZX8Usx+GStU+D80LJTVG4uQ/vPy0R Q0o/HJg9p+KBb97osnj5p3SpaPWuolp6UsidkWigLkFuRhXdNUosG4BeSh0Ou16PGfQJ AvIw== X-Gm-Message-State: AOPr4FWugLeP6LHqvCQhWmv4hEqKCMRsvAw8aA7CVj9ZYhCRwA2zb4csqpDe33XoPKIhQw== X-Received: by 10.25.146.65 with SMTP id u62mr1818698lfd.121.1461705930922; Tue, 26 Apr 2016 14:25:30 -0700 (PDT) Received: from archthink.lan (141.89-11-213.nextgentel.com. [89.11.213.141]) by smtp.gmail.com with ESMTPSA id f11sm163806lfg.22.2016.04.26.14.25.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Apr 2016 14:25:30 -0700 (PDT) From: Joachim Eastwood To: davem@davemloft.net Cc: Joachim Eastwood , marex@denx.de, dinguyen@opensource.altera.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, netdev@vger.kernel.org Subject: [PATCH net-next 4/5] stmmac: dwmac-socfpga: call phy_resume() only in resume callback Date: Tue, 26 Apr 2016 23:24:58 +0200 Message-Id: <1461705899-17015-5-git-send-email-manabian@gmail.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1461705899-17015-1-git-send-email-manabian@gmail.com> References: <1461705899-17015-1-git-send-email-manabian@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Calling phy_resume() should only be need during driver resume to workaround a hardware errata. Signed-off-by: Joachim Eastwood Tested-by: Marek Vasut --- .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 50 ++++++++-------------- 1 file changed, 19 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index ba0b793..ba49d8c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -198,41 +198,11 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac) static int socfpga_dwmac_init(struct platform_device *pdev, void *priv) { struct socfpga_dwmac *dwmac = priv; - struct net_device *ndev = platform_get_drvdata(pdev); - struct stmmac_priv *stpriv = NULL; - int ret = 0; - - if (!ndev) - return -EINVAL; - - stpriv = netdev_priv(ndev); - if (!stpriv) - return -EINVAL; /* Setup the phy mode in the system manager registers according to * devicetree configuration */ - ret = socfpga_dwmac_setup(dwmac); - - /* Before the enet controller is suspended, the phy is suspended. - * This causes the phy clock to be gated. The enet controller is - * resumed before the phy, so the clock is still gated "off" when - * the enet controller is resumed. This code makes sure the phy - * is "resumed" before reinitializing the enet controller since - * the enet controller depends on an active phy clock to complete - * a DMA reset. A DMA reset will "time out" if executed - * with no phy clock input on the Synopsys enet controller. - * Verified through Synopsys Case #8000711656. - * - * Note that the phy clock is also gated when the phy is isolated. - * Phy "suspend" and "isolate" controls are located in phy basic - * control register 0, and can be modified by the phy driver - * framework. - */ - if (stpriv->phydev) - phy_resume(stpriv->phydev); - - return ret; + return socfpga_dwmac_setup(dwmac); } static int socfpga_dwmac_probe(struct platform_device *pdev) @@ -290,6 +260,24 @@ static int socfpga_dwmac_resume(struct device *dev) socfpga_dwmac_init(pdev, priv->plat->bsp_priv); + /* Before the enet controller is suspended, the phy is suspended. + * This causes the phy clock to be gated. The enet controller is + * resumed before the phy, so the clock is still gated "off" when + * the enet controller is resumed. This code makes sure the phy + * is "resumed" before reinitializing the enet controller since + * the enet controller depends on an active phy clock to complete + * a DMA reset. A DMA reset will "time out" if executed + * with no phy clock input on the Synopsys enet controller. + * Verified through Synopsys Case #8000711656. + * + * Note that the phy clock is also gated when the phy is isolated. + * Phy "suspend" and "isolate" controls are located in phy basic + * control register 0, and can be modified by the phy driver + * framework. + */ + if (priv->phydev) + phy_resume(priv->phydev); + return stmmac_resume(dev); } #endif /* CONFIG_PM_SLEEP */