From patchwork Wed Feb 3 14:54:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 578152 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E79FF1401CA for ; Thu, 4 Feb 2016 01:55:08 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Uc1BcMC1; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932974AbcBCOyq (ORCPT ); Wed, 3 Feb 2016 09:54:46 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:35231 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754669AbcBCOym (ORCPT ); Wed, 3 Feb 2016 09:54:42 -0500 Received: by mail-wm0-f67.google.com with SMTP id l66so7775027wml.2; Wed, 03 Feb 2016 06:54:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zANW1XmZ6BXBy7X+eVqxEEGr5JheAh2a1p6lMFt0+yE=; b=Uc1BcMC1wp7Lzc+/seyIiAORD/UwbOg5l0vsCX6LmmcSAYj/v8J0luWcX+C3Lshjae gktXkNqb/e6KTVWYVFldfIHZodOtnmmLNDyvadOKHIvratm2buY38RePTU+g6w/QdUO8 NRjcmHzwJCRVyYWH4lMdXTBZ5lRccVAo+RchuymqREMurgO0+W/VB+LK/PWSgHL1TC+H 1ECNOBrvXBuaS12ALjmr/tm+3aXmW+VYcerN4Vn6MgzoBIbNgRPMdswbsWbyOn3LIadU qxGiBMk3716vVsfcmxXdV5o36wvCx7hCruoNSHZNnSSomaQobSa16b466gOClE1SUjxd PQAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zANW1XmZ6BXBy7X+eVqxEEGr5JheAh2a1p6lMFt0+yE=; b=adgAQaGKLKVnl8USOwFZiT1Yfz3Hy7Qa1EYwuf+F/Aj/Z+8ynSrHoU8M8/gsB+cZ4G A2jjtxee+TFireU7RDC3Kbgq99Wv6B7SotMVIImLxUuUToDqQzK2qJu2aCjgSk6MBTiE KidQOuum/grxVsyOBeOdrHbfC8XAYnR5jXBqos5p0vSM2DmlsqE3qee8lcoviUcyIJdN DtOFt+voOOl2GhPfYee2DDZzr6y2Dvp7b0qUW/qynSOPCjc/tDeZTODA4W1W9/np++UY 2dzmlbrcTUqxOQLMhEZxRzwowj0wGSF1TOyfMh984C5a5O6TOdPhbSMgWR95azGokjir wCYQ== X-Gm-Message-State: AG10YOQSca/vZflIZG6vYASBGOJkXa1YX+68iX/G579T6FTe6Rxt47GCue/IS/Lk0KnX3g== X-Received: by 10.194.114.164 with SMTP id jh4mr2346538wjb.153.1454511280627; Wed, 03 Feb 2016 06:54:40 -0800 (PST) Received: from lmenx29n.st.com. ([80.12.43.25]) by smtp.gmail.com with ESMTPSA id l2sm6901450wjf.15.2016.02.03.06.54.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Feb 2016 06:54:40 -0800 (PST) From: Alexandre TORGUE To: Maxime Coquelin , Giuseppe Cavallaro , netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] net: ethernet: dwmac: add Ethernet glue logic for stm32 chip Date: Wed, 3 Feb 2016 15:54:32 +0100 Message-Id: <1454511275-9791-2-git-send-email-alexandre.torgue@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454511275-9791-1-git-send-email-alexandre.torgue@gmail.com> References: <1454511275-9791-1-git-send-email-alexandre.torgue@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org stm324xx family chips support Synopsys MAC 3.510 IP. This patch adds settings for logical glue logic: -clocks -mode selection MII or RMII. Signed-off-by: Alexandre TORGUE diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index cec147d..a94dd15 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -114,6 +114,18 @@ config DWMAC_SUNXI This selects Allwinner SoC glue layer support for the stmmac device driver. This driver is used for A20/A31 GMAC ethernet controller. + +config DWMAC_STM32 + tristate "STM32 DWMAC support" + default ARCH_STM32 + depends on OF + select MFD_SYSCON + ---help--- + Support for ethernet controller on STM32 SOCs. + + This selects STM32 SoC glue layer support for the stmmac + device driver. This driver is used on for the STM32 series + SOCs GMAC ethernet controller. endif config STMMAC_PCI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index b390161..9fb2061 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-socfpga.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o +obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o stmmac-platform-objs:= stmmac_platform.o obj-$(CONFIG_STMMAC_PCI) += stmmac-pci.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c new file mode 100644 index 0000000..56ccc20 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -0,0 +1,177 @@ +/* + * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU + * + * Copyright (C) Alexandre Torgue 2015 + * Author: Alexandre Torgue + * License terms: GNU General Public License (GPL), version 2 + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +#define MII_PHY_SEL_MASK BIT(23) + +struct stm32_dwmac { + int interface; /* MII interface */ + struct clk *clk_tx; + struct clk *clk_rx; + u32 mode_reg; /* MAC glue-logic mode register */ + struct device *dev; + struct regmap *regmap; + u32 speed; +}; + +static int stm32_dwmac_init(struct platform_device *pdev, void *priv) +{ + struct stm32_dwmac *dwmac = priv; + struct regmap *regmap = dwmac->regmap; + int ret, iface = dwmac->interface; + u32 reg = dwmac->mode_reg; + u32 val; + + if (dwmac->clk_tx) + ret = clk_prepare_enable(dwmac->clk_tx); + if (ret) + goto out; + + if (dwmac->clk_rx) + ret = clk_prepare_enable(dwmac->clk_rx); + if (ret) + goto out_disable_clk_tx; + + val = (iface == PHY_INTERFACE_MODE_MII) ? 0 : 1; + ret = regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, val); + if (ret) + goto out_disable_clk_tx_rx; + + return 0; + +out_disable_clk_tx_rx: + clk_disable_unprepare(dwmac->clk_rx); +out_disable_clk_tx: + clk_disable_unprepare(dwmac->clk_tx); +out: + return ret; +} + +static void stm32_dwmac_exit(struct platform_device *pdev, void *priv) +{ + struct stm32_dwmac *dwmac = priv; + + if (dwmac->clk_tx) + clk_disable_unprepare(dwmac->clk_tx); + if (dwmac->clk_rx) + clk_disable_unprepare(dwmac->clk_rx); +} + +static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct regmap *regmap; + int err; + + if (!np) + return -EINVAL; + + /* Get TX/RX clocks */ + dwmac->clk_tx = devm_clk_get(dev, "tx-clk"); + if (IS_ERR(dwmac->clk_tx)) { + dev_warn(dev, "No tx clock provided...\n"); + dwmac->clk_tx = NULL; + } + dwmac->clk_rx = devm_clk_get(dev, "rx-clk"); + if (IS_ERR(dwmac->clk_rx)) { + dev_warn(dev, "No rx clock provided...\n"); + dwmac->clk_rx = NULL; + } + + /* Get mode register */ + regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); + if (err) { + dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); + return err; + } + + dwmac->dev = dev; + dwmac->interface = of_get_phy_mode(np); + dwmac->regmap = regmap; + + return 0; +} + +static int stm32_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct stm32_dwmac *dwmac; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + ret = stm32_dwmac_parse_data(dwmac, pdev); + if (ret) { + dev_err(&pdev->dev, "Unable to parse OF data\n"); + return ret; + } + + plat_dat->bsp_priv = dwmac; + plat_dat->init = stm32_dwmac_init; + plat_dat->exit = stm32_dwmac_exit; + + ret = stm32_dwmac_init(pdev, plat_dat->bsp_priv); + if (ret) + return ret; + + return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); +} + +static const struct of_device_id stm32_dwmac_match[] = { + { .compatible = "st,stm32-dwmac"}, + { } +}; +MODULE_DEVICE_TABLE(of, stm32_dwmac_match); + +static struct platform_driver stm32_dwmac_driver = { + .probe = stm32_dwmac_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "stm32-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = stm32_dwmac_match, + }, +}; +module_platform_driver(stm32_dwmac_driver); + +MODULE_AUTHOR("Alexandre Torgue "); +MODULE_DESCRIPTION("STMicroelectronics MCU DWMAC Specific Glue layer"); +MODULE_LICENSE("GPL"); +