From patchwork Fri Oct 16 12:01:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiri Pirko X-Patchwork-Id: 531250 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 863311402B4 for ; Fri, 16 Oct 2015 23:02:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754130AbbJPMCC (ORCPT ); Fri, 16 Oct 2015 08:02:02 -0400 Received: from mail-wi0-f182.google.com ([209.85.212.182]:35621 "EHLO mail-wi0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754018AbbJPMB5 (ORCPT ); Fri, 16 Oct 2015 08:01:57 -0400 Received: by wicll6 with SMTP id ll6so6642713wic.0 for ; Fri, 16 Oct 2015 05:01:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6j7tLVK3vKjdTPy/YSDgObsgKxlfE6Q22rlxJnEa0ks=; b=BRCuxYj1OR1BPqq+VHjri5QDKUz9jGd2VPRjFyEUfcevPW82AMP8L+EUkGngQkcLkd FbVuRdY9Wir4IrNlG36ftlT2jCruQQTmVSyAgZTykbNW/UiE50Y8y46J84wxsdLx6eUh /72LU9ywL6HflS2RxNQ8vU2GbujPSp7ddMau/v1A7LuyGDcgsrfUeVSB9KxMe6WB/jq2 BSEsJcUMi5AVBLLhAiEOLJByXO8qdWT82KwglBL+7RHEobk6VmFOT8nj7hAcmNAPj8xS 2aR5f9rIGV9hzJoAxgGp/wGGZmIM5WbZRehy8wvU8Hcx3OKHQf2yqQS4ZkIuDkW/y/AI jkOw== X-Gm-Message-State: ALoCoQnaW2p/ByQRZjNGBeqH3zW3PdXBmsCw/XtIok2MDmu5xkgncMZyQrrKHincnhz+ceYR7wwO X-Received: by 10.194.9.97 with SMTP id y1mr18614953wja.84.1444996916132; Fri, 16 Oct 2015 05:01:56 -0700 (PDT) Received: from localhost (ip-94-113-120-24.net.upcbroadband.cz. [94.113.120.24]) by smtp.gmail.com with ESMTPSA id wz5sm2927208wjc.20.2015.10.16.05.01.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Oct 2015 05:01:55 -0700 (PDT) From: Jiri Pirko To: netdev@vger.kernel.org, ogerlitz@mellanox.com Cc: davem@davemloft.net, idosch@mellanox.com, eladr@mellanox.com, yotamg@mellanox.com, sfeldma@gmail.com, f.fainelli@gmail.com, linux@roeck-us.net, vivien.didelot@savoirfairelinux.com, andrew@lunn.ch, john.fastabend@gmail.com, David.Laight@ACULAB.COM, stephen@networkplumber.org, tgraf@suug.ch, jhs@mojatatu.com, sagir@mellanox.com, mattyk@mellanox.com, aviadr@mellanox.com Subject: [patch net-next 13/16] mlxsw: reg: Add Switch Virtual-Port Enabling register definition Date: Fri, 16 Oct 2015 14:01:34 +0200 Message-Id: <1444996897-2708-14-git-send-email-jiri@resnulli.us> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1444996897-2708-1-git-send-email-jiri@resnulli.us> References: <1444996897-2708-1-git-send-email-jiri@resnulli.us> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ido Schimmel In order for a port to support {Port, VID} to FID mapping it needs to be configured to a virtual port mode (as opposed to VLAN mode). Add the SVPE register, which enables port virtualization. Signed-off-by: Ido Schimmel Signed-off-by: Jiri Pirko --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 5a97707..8e1888b 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -976,6 +976,42 @@ static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, mlxsw_reg_svfa_vid_set(payload, vid); } +/* SVPE - Switch Virtual-Port Enabling Register + * -------------------------------------------- + * Enables port virtualization. + */ +#define MLXSW_REG_SVPE_ID 0x201E +#define MLXSW_REG_SVPE_LEN 0x4 + +static const struct mlxsw_reg_info mlxsw_reg_svpe = { + .id = MLXSW_REG_SVPE_ID, + .len = MLXSW_REG_SVPE_LEN, +}; + +/* reg_svpe_local_port + * Local port number + * Access: Index + * + * Note: CPU port is not supported (uses VLAN mode only). + */ +MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); + +/* reg_svpe_vp_en + * Virtual port enable. + * 0 - Disable, VLAN mode (VID to FID). + * 1 - Enable, Virtual port mode ({Port, VID} to FID). + * Access: RW + */ +MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); + +static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, + bool enable) +{ + MLXSW_REG_ZERO(svpe, payload); + mlxsw_reg_svpe_local_port_set(payload, local_port); + mlxsw_reg_svpe_vp_en_set(payload, enable); +} + /* SFMR - Switch FID Management Register * ------------------------------------- * Creates and configures FIDs. @@ -2241,6 +2277,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id) return "SPMLR"; case MLXSW_REG_SVFA_ID: return "SVFA"; + case MLXSW_REG_SVPE_ID: + return "SVPE"; case MLXSW_REG_SFMR_ID: return "SFMR"; case MLXSW_REG_PMLP_ID: