| Message ID | 1410273070-22485-3-git-send-email-rogerq@ti.com |
|---|---|
| State | Awaiting Upstream, archived |
| Delegated to: | David Miller |
| Headers | show |
On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote: > Some TI SoCs like DRA7 have a RAMINIT register specification > different from the other AMxx SoCs and as expected by the > existing driver. > > To add more insanity, this register is shared with other > IPs like DSS, PCIe and PWM. > > Provides a more generic mechanism to specify the RAMINIT > register location and START/DONE bit position and use the > syscon/regmap framework to access the register. > > Signed-off-by: Roger Quadros <rogerq@ti.com> > --- > .../devicetree/bindings/net/can/c_can.txt | 7 ++ > drivers/net/can/c_can/c_can.h | 11 ++- > drivers/net/can/c_can/c_can_platform.c | 109 +++++++++++++++------ > 3 files changed, 95 insertions(+), 32 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt > index 8f1ae81..e12d1a1 100644 > --- a/Documentation/devicetree/bindings/net/can/c_can.txt > +++ b/Documentation/devicetree/bindings/net/can/c_can.txt > @@ -13,6 +13,13 @@ Optional properties: > - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the > instance number > > +- ti,raminit-syscon : Handle to system control region that contains the > + RAMINIT register. If specified, the second memory resource > + in the reg property must index into the RAMINIT > + register within the syscon region There seems to be a simple "syscon" property these days. > +- ti,raminit-start-bit : Bit posistion of START bit in the RAMINIT register > +- ti,raminit-done-bit : Bit position of DONE bit in the RAMINIT register This should not be encoded in DT! This is not describing hardware setup. The driver should know where the bits are for the syscon phandle, depending on which SoC it runs...
On 09/30/2014 04:26 PM, Wolfram Sang wrote: > On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote: >> Some TI SoCs like DRA7 have a RAMINIT register specification >> different from the other AMxx SoCs and as expected by the >> existing driver. >> >> To add more insanity, this register is shared with other >> IPs like DSS, PCIe and PWM. >> >> Provides a more generic mechanism to specify the RAMINIT >> register location and START/DONE bit position and use the >> syscon/regmap framework to access the register. >> >> Signed-off-by: Roger Quadros <rogerq@ti.com> >> --- >> .../devicetree/bindings/net/can/c_can.txt | 7 ++ >> drivers/net/can/c_can/c_can.h | 11 ++- >> drivers/net/can/c_can/c_can_platform.c | 109 +++++++++++++++------ >> 3 files changed, 95 insertions(+), 32 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt >> index 8f1ae81..e12d1a1 100644 >> --- a/Documentation/devicetree/bindings/net/can/c_can.txt >> +++ b/Documentation/devicetree/bindings/net/can/c_can.txt >> @@ -13,6 +13,13 @@ Optional properties: >> - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the >> instance number >> >> +- ti,raminit-syscon : Handle to system control region that contains the >> + RAMINIT register. If specified, the second memory resource >> + in the reg property must index into the RAMINIT >> + register within the syscon region > > There seems to be a simple "syscon" property these days. I had used plain "syscon" in the earlier revisions but was asked to make it a TI specific property since only TI uses this mechanism. > >> +- ti,raminit-start-bit : Bit posistion of START bit in the RAMINIT register >> +- ti,raminit-done-bit : Bit position of DONE bit in the RAMINIT register > > This should not be encoded in DT! This is not describing hardware setup. > The driver should know where the bits are for the syscon phandle, > depending on which SoC it runs... > OK. I'll think of matching the compatible ID with SOC specific data in the driver. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 09/30/2014 03:26 PM, Wolfram Sang wrote: > On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote: >> Some TI SoCs like DRA7 have a RAMINIT register specification >> different from the other AMxx SoCs and as expected by the >> existing driver. >> >> To add more insanity, this register is shared with other >> IPs like DSS, PCIe and PWM. >> >> Provides a more generic mechanism to specify the RAMINIT >> register location and START/DONE bit position and use the >> syscon/regmap framework to access the register. >> >> Signed-off-by: Roger Quadros <rogerq@ti.com> >> --- >> .../devicetree/bindings/net/can/c_can.txt | 7 ++ >> drivers/net/can/c_can/c_can.h | 11 ++- >> drivers/net/can/c_can/c_can_platform.c | 109 +++++++++++++++------ >> 3 files changed, 95 insertions(+), 32 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt >> index 8f1ae81..e12d1a1 100644 >> --- a/Documentation/devicetree/bindings/net/can/c_can.txt >> +++ b/Documentation/devicetree/bindings/net/can/c_can.txt >> @@ -13,6 +13,13 @@ Optional properties: >> - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the >> instance number >> >> +- ti,raminit-syscon : Handle to system control region that contains the >> + RAMINIT register. If specified, the second memory resource >> + in the reg property must index into the RAMINIT >> + register within the syscon region > > There seems to be a simple "syscon" property these days. > >> +- ti,raminit-start-bit : Bit posistion of START bit in the RAMINIT register >> +- ti,raminit-done-bit : Bit position of DONE bit in the RAMINIT register > > This should not be encoded in DT! This is not describing hardware setup. > The driver should know where the bits are for the syscon phandle, > depending on which SoC it runs... Is the register shared by more than one core? If so the information has to go somewhere. Using an alias in the DT is probably the wrong approach. Marc
> >> +- ti,raminit-syscon : Handle to system control region that contains the > >> + RAMINIT register. If specified, the second memory resource > >> + in the reg property must index into the RAMINIT > >> + register within the syscon region > > > > There seems to be a simple "syscon" property these days. > > I had used plain "syscon" in the earlier revisions but was asked to make it a TI specific > property since only TI uses this mechanism. I see, when was that? Currently, it looks messy :( Grepping through the dts files in 3.17-rc7, I see that bcm7445 uses "syscon" and variants with prefixes, STE uses it, too. Samsung uses "samsung,syscon-phandle", st uses "st,syscon"... The MACID readout patches for AM335x (just applied right now) also use "syscon": https://patchwork.ozlabs.org/patch/394289/ I'd vote for a generic "syscon" to be OK, yet I guess the DT maintainers will have the final word. > >> +- ti,raminit-start-bit : Bit posistion of START bit in the RAMINIT register > >> +- ti,raminit-done-bit : Bit position of DONE bit in the RAMINIT register > > > > This should not be encoded in DT! This is not describing hardware setup. > > The driver should know where the bits are for the syscon phandle, > > depending on which SoC it runs... > > > OK. I'll think of matching the compatible ID with SOC specific data in the driver. Great, thanks!
On 09/30/2014 04:52 PM, Wolfram Sang wrote: > >>>> +- ti,raminit-syscon : Handle to system control region that contains the >>>> + RAMINIT register. If specified, the second memory resource >>>> + in the reg property must index into the RAMINIT >>>> + register within the syscon region >>> >>> There seems to be a simple "syscon" property these days. >> >> I had used plain "syscon" in the earlier revisions but was asked to make it a TI specific >> property since only TI uses this mechanism. > > I see, when was that? Currently, it looks messy :( Grepping through the > dts files in 3.17-rc7, I see that bcm7445 uses "syscon" and variants > with prefixes, STE uses it, too. Samsung uses "samsung,syscon-phandle", > st uses "st,syscon"... > > The MACID readout patches for AM335x (just applied right now) also use > "syscon": https://patchwork.ozlabs.org/patch/394289/ > > I'd vote for a generic "syscon" to be OK, yet I guess the DT maintainers > will have the final word. Now that I actually checked, it was never just "syscon" but just without the "ti" vendor prefix. Sorry for the misinformation. As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"? cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 09/30/2014 04:45 PM, Marc Kleine-Budde wrote: > On 09/30/2014 03:26 PM, Wolfram Sang wrote: >> On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote: >>> Some TI SoCs like DRA7 have a RAMINIT register specification >>> different from the other AMxx SoCs and as expected by the >>> existing driver. >>> >>> To add more insanity, this register is shared with other >>> IPs like DSS, PCIe and PWM. >>> >>> Provides a more generic mechanism to specify the RAMINIT >>> register location and START/DONE bit position and use the >>> syscon/regmap framework to access the register. >>> >>> Signed-off-by: Roger Quadros <rogerq@ti.com> >>> --- >>> .../devicetree/bindings/net/can/c_can.txt | 7 ++ >>> drivers/net/can/c_can/c_can.h | 11 ++- >>> drivers/net/can/c_can/c_can_platform.c | 109 +++++++++++++++------ >>> 3 files changed, 95 insertions(+), 32 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt >>> index 8f1ae81..e12d1a1 100644 >>> --- a/Documentation/devicetree/bindings/net/can/c_can.txt >>> +++ b/Documentation/devicetree/bindings/net/can/c_can.txt >>> @@ -13,6 +13,13 @@ Optional properties: >>> - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the >>> instance number >>> >>> +- ti,raminit-syscon : Handle to system control region that contains the >>> + RAMINIT register. If specified, the second memory resource >>> + in the reg property must index into the RAMINIT >>> + register within the syscon region >> >> There seems to be a simple "syscon" property these days. >> >>> +- ti,raminit-start-bit : Bit posistion of START bit in the RAMINIT register >>> +- ti,raminit-done-bit : Bit position of DONE bit in the RAMINIT register >> >> This should not be encoded in DT! This is not describing hardware setup. >> The driver should know where the bits are for the syscon phandle, >> depending on which SoC it runs... > > Is the register shared by more than one core? If so the information has > to go somewhere. Using an alias in the DT is probably the wrong approach. In case of the DRA7xx Soc, this syscon register is shared by multiple cores. (CAN, Display, etc), sigh!! For AM335x and AM43xx SoCs, the register is used only for DCAN. but shared by 2 DCAN instances. Shouldn't the information for the CAN specific bits lie in the CAN driver? cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 09/30/2014 04:02 PM, Roger Quadros wrote: > On 09/30/2014 04:45 PM, Marc Kleine-Budde wrote: >> On 09/30/2014 03:26 PM, Wolfram Sang wrote: >>> On Tue, Sep 09, 2014 at 05:31:09PM +0300, Roger Quadros wrote: >>>> Some TI SoCs like DRA7 have a RAMINIT register specification >>>> different from the other AMxx SoCs and as expected by the >>>> existing driver. >>>> >>>> To add more insanity, this register is shared with other >>>> IPs like DSS, PCIe and PWM. >>>> >>>> Provides a more generic mechanism to specify the RAMINIT >>>> register location and START/DONE bit position and use the >>>> syscon/regmap framework to access the register. >>>> >>>> Signed-off-by: Roger Quadros <rogerq@ti.com> >>>> --- >>>> .../devicetree/bindings/net/can/c_can.txt | 7 ++ >>>> drivers/net/can/c_can/c_can.h | 11 ++- >>>> drivers/net/can/c_can/c_can_platform.c | 109 +++++++++++++++------ >>>> 3 files changed, 95 insertions(+), 32 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt >>>> index 8f1ae81..e12d1a1 100644 >>>> --- a/Documentation/devicetree/bindings/net/can/c_can.txt >>>> +++ b/Documentation/devicetree/bindings/net/can/c_can.txt >>>> @@ -13,6 +13,13 @@ Optional properties: >>>> - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the >>>> instance number >>>> >>>> +- ti,raminit-syscon : Handle to system control region that contains the >>>> + RAMINIT register. If specified, the second memory resource >>>> + in the reg property must index into the RAMINIT >>>> + register within the syscon region >>> >>> There seems to be a simple "syscon" property these days. >>> >>>> +- ti,raminit-start-bit : Bit posistion of START bit in the RAMINIT register >>>> +- ti,raminit-done-bit : Bit position of DONE bit in the RAMINIT register >>> >>> This should not be encoded in DT! This is not describing hardware setup. >>> The driver should know where the bits are for the syscon phandle, >>> depending on which SoC it runs... >> >> Is the register shared by more than one core? If so the information has >> to go somewhere. Using an alias in the DT is probably the wrong approach. > > In case of the DRA7xx Soc, this syscon register is shared by multiple cores. (CAN, Display, etc), sigh!! > For AM335x and AM43xx SoCs, the register is used only for DCAN. but shared by 2 DCAN instances. > > Shouldn't the information for the CAN specific bits lie in the CAN driver? As there are more than one DCAN instance on the same SOC the information which DCAN instance uses which bits in the register has to go somewhere. We might add these bits as the 3rd and 4th parameter to the syscon phandle. Marc
> As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"?
Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we
need an (optional) way to describe that. However, accessing syscon
registers in general is not TI specific and a generic way to do this
should be used. Which looks to me like the "syscon" property to allow
access to the register. Still, we should ask DT maintainers about it,
maybe they prefer a more precise property like "syscon-raminit" to allow
for further syscon extensions later or something...
On 09/30/2014 04:19 PM, Wolfram Sang wrote: > >> As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"? > > Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we > need an (optional) way to describe that. However, accessing syscon > registers in general is not TI specific and a generic way to do this > should be used. Which looks to me like the "syscon" property to allow > access to the register. Still, we should ask DT maintainers about it, > maybe they prefer a more precise property like "syscon-raminit" to allow > for further syscon extensions later or something... What do you think about putting the bit information in the syscon-raminit phandle as additional arguments? Marc
On Tue, Sep 30, 2014 at 04:22:08PM +0200, Marc Kleine-Budde wrote: > On 09/30/2014 04:19 PM, Wolfram Sang wrote: > > > >> As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"? > > > > Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we > > need an (optional) way to describe that. However, accessing syscon > > registers in general is not TI specific and a generic way to do this > > should be used. Which looks to me like the "syscon" property to allow > > access to the register. Still, we should ask DT maintainers about it, > > maybe they prefer a more precise property like "syscon-raminit" to allow > > for further syscon extensions later or something... > > What do you think about putting the bit information in the > syscon-raminit phandle as additional arguments? Then we'd have <n> syscon phandles for <n> instances? Also, judging from Markus patch [1] there is already some infrastructure, namely syscon_regmap_lookup_by_phandle(). From a glimpse, it doesn't look viable to add such a support to it. So, I'd rather drop additional arguments. Why would you like to have it encoded in DT?
On 09/30/2014 04:49 PM, Wolfram Sang wrote: > On Tue, Sep 30, 2014 at 04:22:08PM +0200, Marc Kleine-Budde wrote: >> On 09/30/2014 04:19 PM, Wolfram Sang wrote: >>> >>>> As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"? >>> >>> Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we >>> need an (optional) way to describe that. However, accessing syscon >>> registers in general is not TI specific and a generic way to do this >>> should be used. Which looks to me like the "syscon" property to allow >>> access to the register. Still, we should ask DT maintainers about it, >>> maybe they prefer a more precise property like "syscon-raminit" to allow >>> for further syscon extensions later or something... >> >> What do you think about putting the bit information in the >> syscon-raminit phandle as additional arguments? > > Then we'd have <n> syscon phandles for <n> instances? > > Also, judging from Markus patch [1] there is already some > infrastructure, namely syscon_regmap_lookup_by_phandle(). From a > glimpse, it doesn't look viable to add such a support to it. Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at: drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits. > So, I'd rather drop additional arguments. > > Why would you like to have it encoded in DT? Where put the information then? Into the driver, but where do you get the reference which instance of the DCAN you are, so that you can look up the correct bits? Marc
> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for > additional parameters. Have a look at: > > drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c > > First get the regmap, then the 1st argument is the offset in the regmap, > the 2nd and 3rd could be the bits. So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift> Phew... Then we should really have a "syscon-raminit" property probably, so that at least plain "syscon" has a consistent syntax? > > > So, I'd rather drop additional arguments. > > > > Why would you like to have it encoded in DT? > > Where put the information then? Into the driver, but where do you get > the reference which instance of the DCAN you are, so that you can look > up the correct bits? Agreed. I thought we had this information in the driver already, but we haven't...
On 09/30/2014 05:25 PM, Wolfram Sang wrote: > >> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for >> additional parameters. Have a look at: >> >> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c >> >> First get the regmap, then the 1st argument is the offset in the regmap, >> the 2nd and 3rd could be the bits. > > So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> > For another driver (the stmmac example): <reg_offset> <reg_shift> The DCAN's "reg" is a "reg_offset" as in the stmmc. Roger, can we derive both start and done bit from a common reg_shift? > Phew... Then we should really have a "syscon-raminit" property probably, > so that at least plain "syscon" has a consistent syntax? I think^whope we can have the same syntax as the stmmc :D >>> So, I'd rather drop additional arguments. >>> >>> Why would you like to have it encoded in DT? >> >> Where put the information then? Into the driver, but where do you get >> the reference which instance of the DCAN you are, so that you can look >> up the correct bits? > > Agreed. I thought we had this information in the driver already, but we > haven't... > The current driver relies on the of_alias_get_id(), which isn't considered best practice, is it? So I want to avoid this when switching to syscon. Marc
On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote: > On 09/30/2014 05:25 PM, Wolfram Sang wrote: >> >>> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for >>> additional parameters. Have a look at: >>> >>> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c >>> >>> First get the regmap, then the 1st argument is the offset in the regmap, >>> the 2nd and 3rd could be the bits. >> >> So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> >> For another driver (the stmmac example): <reg_offset> <reg_shift> > > The DCAN's "reg" is a "reg_offset" as in the stmmc. > > Roger, can we derive both start and done bit from a common reg_shift? I'm sorry I didn't understand what you meant. <&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. Even though reg offset is the same for both the DCAN instances. > >> Phew... Then we should really have a "syscon-raminit" property probably, >> so that at least plain "syscon" has a consistent syntax? > > I think^whope we can have the same syntax as the stmmc :D I agree too. > >>>> So, I'd rather drop additional arguments. >>>> >>>> Why would you like to have it encoded in DT? >>> >>> Where put the information then? Into the driver, but where do you get >>> the reference which instance of the DCAN you are, so that you can look >>> up the correct bits? >> >> Agreed. I thought we had this information in the driver already, but we >> haven't... >> > > The current driver relies on the of_alias_get_id(), which isn't > considered best practice, is it? So I want to avoid this when switching > to syscon. cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/01/2014 10:45 AM, Roger Quadros wrote: > On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote: >> On 09/30/2014 05:25 PM, Wolfram Sang wrote: >>> >>>> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for >>>> additional parameters. Have a look at: >>>> >>>> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c >>>> >>>> First get the regmap, then the 1st argument is the offset in the regmap, >>>> the 2nd and 3rd could be the bits. >>> >>> So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> >>> For another driver (the stmmac example): <reg_offset> <reg_shift> >> >> The DCAN's "reg" is a "reg_offset" as in the stmmc. >> >> Roger, can we derive both start and done bit from a common reg_shift? > > I'm sorry I didn't understand what you meant. > > <&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. > Even though reg offset is the same for both the DCAN instances. What's start bit and stop bit for instance 0 and 1 on that SoC that has two instances?? Marc
On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote: > On 10/01/2014 10:45 AM, Roger Quadros wrote: >> On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote: >>> On 09/30/2014 05:25 PM, Wolfram Sang wrote: >>>> >>>>> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for >>>>> additional parameters. Have a look at: >>>>> >>>>> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c >>>>> >>>>> First get the regmap, then the 1st argument is the offset in the regmap, >>>>> the 2nd and 3rd could be the bits. >>>> >>>> So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> >>>> For another driver (the stmmac example): <reg_offset> <reg_shift> >>> >>> The DCAN's "reg" is a "reg_offset" as in the stmmc. >>> >>> Roger, can we derive both start and done bit from a common reg_shift? >> >> I'm sorry I didn't understand what you meant. >> >> <&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. >> Even though reg offset is the same for both the DCAN instances. > > What's start bit and stop bit for instance 0 and 1 on that SoC that has > two instances?? > we have 3 SoCs at the moment, all have 2 DCAN instances. AM33xx & AM43xx instance start stop 1 0 8 2 1 9 DRA7xx instance start stop 1 3 1 2 5 2 cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/01/2014 11:06 AM, Roger Quadros wrote: > On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote: >> On 10/01/2014 10:45 AM, Roger Quadros wrote: >>> On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote: >>>> On 09/30/2014 05:25 PM, Wolfram Sang wrote: >>>>> >>>>>> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for >>>>>> additional parameters. Have a look at: >>>>>> >>>>>> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c >>>>>> >>>>>> First get the regmap, then the 1st argument is the offset in the regmap, >>>>>> the 2nd and 3rd could be the bits. >>>>> >>>>> So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> >>>>> For another driver (the stmmac example): <reg_offset> <reg_shift> >>>> >>>> The DCAN's "reg" is a "reg_offset" as in the stmmc. >>>> >>>> Roger, can we derive both start and done bit from a common reg_shift? >>> >>> I'm sorry I didn't understand what you meant. >>> >>> <&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. >>> Even though reg offset is the same for both the DCAN instances. >> >> What's start bit and stop bit for instance 0 and 1 on that SoC that has >> two instances? >> > > we have 3 SoCs at the moment, all have 2 DCAN instances. > > AM33xx & AM43xx > instance start stop > 1 0 8 > 2 1 9 If we use a 0-based numbering for the instances: instance start stop 0 (0 << instance) (8 << instance) 1 (0 << instance) (8 << instance) > DRA7xx > instance start stop > 1 3 1 > 2 5 2 ^ 5 or 4? Marc
On 10/01/2014 01:01 PM, Marc Kleine-Budde wrote: > On 10/01/2014 11:06 AM, Roger Quadros wrote: >> On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote: >>> On 10/01/2014 10:45 AM, Roger Quadros wrote: >>>> On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote: >>>>> On 09/30/2014 05:25 PM, Wolfram Sang wrote: >>>>>> >>>>>>> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for >>>>>>> additional parameters. Have a look at: >>>>>>> >>>>>>> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c >>>>>>> >>>>>>> First get the regmap, then the 1st argument is the offset in the regmap, >>>>>>> the 2nd and 3rd could be the bits. >>>>>> >>>>>> So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> >>>>>> For another driver (the stmmac example): <reg_offset> <reg_shift> >>>>> >>>>> The DCAN's "reg" is a "reg_offset" as in the stmmc. >>>>> >>>>> Roger, can we derive both start and done bit from a common reg_shift? >>>> >>>> I'm sorry I didn't understand what you meant. >>>> >>>> <&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. >>>> Even though reg offset is the same for both the DCAN instances. >>> >>> What's start bit and stop bit for instance 0 and 1 on that SoC that has >>> two instances? >>> >> >> we have 3 SoCs at the moment, all have 2 DCAN instances. >> >> AM33xx & AM43xx >> instance start stop >> 1 0 8 >> 2 1 9 > > If we use a 0-based numbering for the instances: > instance start stop > 0 (0 << instance) (8 << instance) > 1 (0 << instance) (8 << instance) > How does the instance number get set? What happens on boards where the first instance is unused while the second one is in use? >> DRA7xx >> instance start stop >> 1 3 1 >> 2 5 2 > ^ > 5 or 4? Unfortunately it is 5 ;) We have display IP related bit in between 3 and 5 :P cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/01/2014 12:12 PM, Roger Quadros wrote: > On 10/01/2014 01:01 PM, Marc Kleine-Budde wrote: >> On 10/01/2014 11:06 AM, Roger Quadros wrote: >>> On 10/01/2014 11:47 AM, Marc Kleine-Budde wrote: >>>> On 10/01/2014 10:45 AM, Roger Quadros wrote: >>>>> On 09/30/2014 07:04 PM, Marc Kleine-Budde wrote: >>>>>> On 09/30/2014 05:25 PM, Wolfram Sang wrote: >>>>>>> >>>>>>>> Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for >>>>>>>> additional parameters. Have a look at: >>>>>>>> >>>>>>>> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c >>>>>>>> >>>>>>>> First get the regmap, then the 1st argument is the offset in the regmap, >>>>>>>> the 2nd and 3rd could be the bits. >>>>>>> >>>>>>> So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> >>>>>>> For another driver (the stmmac example): <reg_offset> <reg_shift> >>>>>> >>>>>> The DCAN's "reg" is a "reg_offset" as in the stmmc. >>>>>> >>>>>> Roger, can we derive both start and done bit from a common reg_shift? >>>>> >>>>> I'm sorry I didn't understand what you meant. >>>>> >>>>> <&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. >>>>> Even though reg offset is the same for both the DCAN instances. >>>> >>>> What's start bit and stop bit for instance 0 and 1 on that SoC that has >>>> two instances? >>>> >>> >>> we have 3 SoCs at the moment, all have 2 DCAN instances. >>> >>> AM33xx & AM43xx >>> instance start stop >>> 1 0 8 >>> 2 1 9 >> >> If we use a 0-based numbering for the instances: >> instance start stop >> 0 (0 << instance) (8 << instance) >> 1 (0 << instance) (8 << instance) >> > > How does the instance number get set? What happens on boards where > the first instance is unused while the second one is in use? Via a single "instance" parameter of the syscon phandle.... > >>> DRA7xx >>> instance start stop >>> 1 3 1 >>> 2 5 2 >> ^ >> 5 or 4? > > Unfortunately it is 5 ;) > We have display IP related bit in between 3 and 5 :P What on earth were the HW engineers thinking???????????? ...if we just have the instance parameter in the syscon phandle, we have to put the mapping into the driver, which makes IMHO no sense, because you have to touch the driver, if there is another SoC with the DCAN core. AFAICS we have these options: 1) syscon phandle with three parameters: reg offset, start bit shift, stop bit shift (the name of the syscon phandle is a different topic) 2) a single ti,start-stop-bit option with two parameter 3) two ti,* entries with a single parameter each (as in Roger's initial patch) Wolfram, which solution do you prefer? I'm in favour of 3 (+ plus a phandle with a reg offset parameter). puzzled, Marc
> > Unfortunately it is 5 ;) > > We have display IP related bit in between 3 and 5 :P > > What on earth were the HW engineers thinking???????????? "Let's test my RNG on the bit-placement of this register" :) > ...if we just have the instance parameter in the syscon phandle, we have > to put the mapping into the driver, which makes IMHO no sense, because > you have to touch the driver, if there is another SoC with the DCAN core. ... which would be my preferred solution. I think new SoCs should have some kind of: compatible = "commodore,c64ultra", "bosch,d_can"; in the DT anyhow to allow for SoC specific quirks/adjustments. And custom raminit belongs to that IMO (see the ti routine getting more and more specific).
On 10/01/2014 01:43 PM, Wolfram Sang wrote: > >>> Unfortunately it is 5 ;) >>> We have display IP related bit in between 3 and 5 :P >> >> What on earth were the HW engineers thinking???????????? > > "Let's test my RNG on the bit-placement of this register" :) :D > >> ...if we just have the instance parameter in the syscon phandle, we have >> to put the mapping into the driver, which makes IMHO no sense, because >> you have to touch the driver, if there is another SoC with the DCAN core. My guess is that TI won't come up with a 3rd variant so we won't have to touch the driver, but you never know for sure. > > ... which would be my preferred solution. I think new SoCs should have > some kind of: > > compatible = "commodore,c64ultra", "bosch,d_can"; > > in the DT anyhow to allow for SoC specific quirks/adjustments. And > custom raminit belongs to that IMO (see the ti routine getting more and > more specific). > Right. For now we need 2 start/stop definations for the existing TI Socs. but where to store the raminit start/stop bits? The driver_data currently seems to contain the CAN type C_CAN vs D_CAN without containing it in a platform_data structure. Is it OK to create a new platform_data structure for CAN and put the type and raminit start/stop bits there? cheers, -roger -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/01/2014 12:57 PM, Roger Quadros wrote: >>> ...if we just have the instance parameter in the syscon phandle, we have >>> to put the mapping into the driver, which makes IMHO no sense, because >>> you have to touch the driver, if there is another SoC with the DCAN core. > > My guess is that TI won't come up with a 3rd variant so we won't have > to touch the driver, but you never know for sure. When I comes to 99% compatible hardware.... I've seen some. >> ... which would be my preferred solution. I think new SoCs should have >> some kind of: >> >> compatible = "commodore,c64ultra", "bosch,d_can"; >> >> in the DT anyhow to allow for SoC specific quirks/adjustments. And >> custom raminit belongs to that IMO (see the ti routine getting more and >> more specific). >> > > Right. For now we need 2 start/stop definations for the existing TI Socs. > > but where to store the raminit start/stop bits? The driver_data currently seems to > contain the CAN type C_CAN vs D_CAN without containing it in a platform_data structure. > > Is it OK to create a new platform_data structure for CAN and put the type and raminit start/stop > bits there? Yes, have a look how it's handled in the flexcan driver. regards, Marc
> Is it OK to create a new platform_data structure for CAN and put the type and raminit start/stop > bits there? I'd say yes, don't see a reason not to.
On 10/01/2014 12:43 PM, Wolfram Sang wrote:
> compatible = "commodore,c64ultra", "bosch,d_can";
\o/
diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt index 8f1ae81..e12d1a1 100644 --- a/Documentation/devicetree/bindings/net/can/c_can.txt +++ b/Documentation/devicetree/bindings/net/can/c_can.txt @@ -13,6 +13,13 @@ Optional properties: - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the instance number +- ti,raminit-syscon : Handle to system control region that contains the + RAMINIT register. If specified, the second memory resource + in the reg property must index into the RAMINIT + register within the syscon region +- ti,raminit-start-bit : Bit posistion of START bit in the RAMINIT register +- ti,raminit-done-bit : Bit position of DONE bit in the RAMINIT register + Note: "ti,hwmods" field is used to fetch the base address and irq resources from TI, omap hwmod data base during device registration. Future plan is to migrate hwmod data base contents into device tree diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h index 99ad1aa..bf68822 100644 --- a/drivers/net/can/c_can/c_can.h +++ b/drivers/net/can/c_can/c_can.h @@ -169,6 +169,14 @@ enum c_can_dev_id { BOSCH_D_CAN, }; +/* Out of band RAMINIT register access via syscon regmap */ +struct c_can_raminit { + struct regmap *syscon; /* for raminit ctrl. reg. access */ + unsigned int reg; /* register index within syscon */ + u8 start_bit; /* START bit position in raminit reg. */ + u8 done_bit; /* DONE bit position in raminit reg. */ +}; + /* c_can private data structure */ struct c_can_priv { struct can_priv can; /* must be the first member */ @@ -186,8 +194,7 @@ struct c_can_priv { const u16 *regs; void *priv; /* for board-specific data */ enum c_can_dev_id type; - u32 __iomem *raminit_ctrlreg; - int instance; + struct c_can_raminit raminit_sys; /* RAMINIT via syscon regmap */ void (*raminit) (const struct c_can_priv *priv, bool enable); u32 comm_rcv_high; u32 rxmasked; diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c index b144e71..fb0c35b 100644 --- a/drivers/net/can/c_can/c_can_platform.c +++ b/drivers/net/can/c_can/c_can_platform.c @@ -32,14 +32,13 @@ #include <linux/clk.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> #include <linux/can/dev.h> #include "c_can.h" -#define CAN_RAMINIT_START_MASK(i) (0x001 << (i)) -#define CAN_RAMINIT_DONE_MASK(i) (0x100 << (i)) -#define CAN_RAMINIT_ALL_MASK(i) (0x101 << (i)) #define DCAN_RAM_INIT_BIT (1 << 3) static DEFINE_SPINLOCK(raminit_lock); /* @@ -72,48 +71,59 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, writew(val, priv->base + 2 * priv->regs[index]); } -static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask, - u32 val) +static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv, + u32 mask, u32 val) { int timeout = 0; + const struct c_can_raminit *raminit = &priv->raminit_sys; + u32 ctrl; + /* We look only at the bits of our instance. */ val &= mask; - while ((readl(priv->raminit_ctrlreg) & mask) != val) { + do { udelay(1); timeout++; + regmap_read(raminit->syscon, raminit->reg, &ctrl); if (timeout == 1000) { dev_err(&priv->dev->dev, "%s: time out\n", __func__); break; } - } + } while ((ctrl & mask) != val); } -static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable) +static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable) { - u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance); + u32 mask; u32 ctrl; + const struct c_can_raminit *raminit = &priv->raminit_sys; spin_lock(&raminit_lock); - ctrl = readl(priv->raminit_ctrlreg); + mask = 1 << raminit->start_bit | 1 << raminit->done_bit; + regmap_read(raminit->syscon, raminit->reg, &ctrl); + /* We clear the done and start bit first. The start bit is * looking at the 0 -> transition, but is not self clearing; * And we clear the init done bit as well. + * NOTE: DONE must be written with 1 to clear it. */ - ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance); - ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); - writel(ctrl, priv->raminit_ctrlreg); - ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance); - c_can_hw_raminit_wait_ti(priv, mask, ctrl); + ctrl &= ~(1 << raminit->start_bit); + ctrl |= 1 << raminit->done_bit; + regmap_write(raminit->syscon, raminit->reg, ctrl); + + ctrl &= ~(1 << raminit->done_bit); + c_can_hw_raminit_wait_syscon(priv, mask, ctrl); if (enable) { /* Set start bit and wait for the done bit. */ - ctrl |= CAN_RAMINIT_START_MASK(priv->instance); - writel(ctrl, priv->raminit_ctrlreg); - ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); - c_can_hw_raminit_wait_ti(priv, mask, ctrl); + ctrl |= 1 << raminit->start_bit; + regmap_write(raminit->syscon, raminit->reg, ctrl); + + ctrl |= 1 << raminit->done_bit; + c_can_hw_raminit_wait_syscon(priv, mask, ctrl); } + spin_unlock(&raminit_lock); } @@ -202,6 +212,8 @@ static int c_can_plat_probe(struct platform_device *pdev) struct resource *mem, *res; int irq; struct clk *clk; + struct device_node *np = pdev->dev.of_node; + u32 val; if (pdev->dev.of_node) { match = of_match_device(c_can_of_table, &pdev->dev); @@ -271,11 +283,6 @@ static int c_can_plat_probe(struct platform_device *pdev) priv->read_reg32 = d_can_plat_read_reg32; priv->write_reg32 = d_can_plat_write_reg32; - if (pdev->dev.of_node) - priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can"); - else - priv->instance = pdev->id; - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); /* Not all D_CAN modules have a separate register for the D_CAN * RAM initialization. Use default RAM init bit in D_CAN module @@ -286,12 +293,54 @@ static int c_can_plat_probe(struct platform_device *pdev) break; } - priv->raminit_ctrlreg = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (!priv->raminit_ctrlreg || priv->instance < 0) - dev_info(&pdev->dev, "control memory is not used for raminit\n"); - else - priv->raminit = c_can_hw_raminit_ti; + /* If separate RAMINIT register is specified access + * it using syscon regmap. Mostly for TI platforms. + */ + ret = -EINVAL; + if (!np) { + dev_err(&pdev->dev, + "separate RAMINIT reg. not supported on non DT\n"); + goto exit_free_device; + } + + priv->raminit_sys.syscon = syscon_regmap_lookup_by_phandle(np, + "ti,raminit-syscon"); + if (IS_ERR(priv->raminit_sys.syscon)) { + dev_err(&pdev->dev, + "couldn't get syscon regmap for RAMINIT reg.\n"); + goto exit_free_device; + } + + priv->raminit_sys.reg = res->start; + if (of_property_read_u32(np, "ti,raminit-start-bit", + &val)) { + dev_err(&pdev->dev, + "missing ti,raminit-start-bit property\n"); + goto exit_free_device; + } + + if (val > 31) { + dev_err(&pdev->dev, + "invalid ti,raminit-start-bit property\n"); + goto exit_free_device; + } + + priv->raminit_sys.start_bit = val; + if (of_property_read_u32(np, "ti,raminit-done-bit", + &val)) { + dev_err(&pdev->dev, + "missing ti,raminit-done-bit property\n"); + goto exit_free_device; + } + + if (val > 31) { + dev_err(&pdev->dev, + "invalid ti,raminit-done-bit property\n"); + goto exit_free_device; + } + + priv->raminit_sys.done_bit = val; + priv->raminit = c_can_hw_raminit_syscon; break; default: ret = -EINVAL;
Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver. To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM. Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register. Signed-off-by: Roger Quadros <rogerq@ti.com> --- .../devicetree/bindings/net/can/c_can.txt | 7 ++ drivers/net/can/c_can/c_can.h | 11 ++- drivers/net/can/c_can/c_can_platform.c | 109 +++++++++++++++------ 3 files changed, 95 insertions(+), 32 deletions(-)