From patchwork Mon Feb 17 10:53:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Manoil X-Patchwork-Id: 320930 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BA4292C00CE for ; Mon, 17 Feb 2014 21:54:36 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752880AbaBQKy2 (ORCPT ); Mon, 17 Feb 2014 05:54:28 -0500 Received: from tx2ehsobe001.messaging.microsoft.com ([65.55.88.11]:50716 "EHLO tx2outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752128AbaBQKxu (ORCPT ); Mon, 17 Feb 2014 05:53:50 -0500 Received: from mail42-tx2-R.bigfish.com (10.9.14.245) by TX2EHSOBE011.bigfish.com (10.9.40.31) with Microsoft SMTP Server id 14.1.225.22; Mon, 17 Feb 2014 10:53:49 +0000 Received: from mail42-tx2 (localhost [127.0.0.1]) by mail42-tx2-R.bigfish.com (Postfix) with ESMTP id EC4F21A00BE; Mon, 17 Feb 2014 10:53:48 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh1155h) Received: from mail42-tx2 (localhost.localdomain [127.0.0.1]) by mail42-tx2 (MessageSwitch) id 1392634426133738_5257; Mon, 17 Feb 2014 10:53:46 +0000 (UTC) Received: from TX2EHSMHS021.bigfish.com (unknown [10.9.14.228]) by mail42-tx2.bigfish.com (Postfix) with ESMTP id 101A63C004F; Mon, 17 Feb 2014 10:53:46 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS021.bigfish.com (10.9.99.121) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 17 Feb 2014 10:53:46 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.158.2; Mon, 17 Feb 2014 10:53:45 +0000 Received: from fsr-fed1764-016.ea.freescale.net (fsr-fed1764-016.ea.freescale.net [10.171.81.161]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s1HArakT030727; Mon, 17 Feb 2014 03:53:44 -0700 From: Claudiu Manoil To: CC: "David S. Miller" Subject: [PATCH net-next v2 5/6] gianfar: Add missing graceful reset steps and fixes Date: Mon, 17 Feb 2014 12:53:18 +0200 Message-ID: <1392634399-5456-6-git-send-email-claudiu.manoil@freescale.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1392634399-5456-1-git-send-email-claudiu.manoil@freescale.com> References: <1392634399-5456-1-git-send-email-claudiu.manoil@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org gfar_halt() and gfar_start() are responsible for stopping and starting the DMA and the Rx/Tx hw rings. They implement the support for the "graceful Rx/Tx stop/start" hw procedure, and also disable/enable eTSEC's hw interrupts in the process. The GRS/GTS procedure requires however to have the RQUEUE/TQUEUE registers cleared first and to wait for a period of time for the current frame to pass through the interface (around ~10ms for a jumbo frame). Only then may the GTS and GRS bits from DMACTRL be set to shut down the DMA, and finally the Tx_EN and Rx_EN bits in MACCFG1 may be cleared to disable the Tx/Rx blocks. The same register programming order applies to start the Rx/Tx: enabling the RQUEUE/TQUEUE *before* clearing the GRS/GTS bits. This is a HW recommendation in order to avoid a possible controller "lock up" during graceful reset. Cleanup the gfar_halt()/start() prototypes, to take priv instead of ndev as their purpose is to operate on HW. Enabling the RQUEUE/TQUEUE in the hw_init() is not needed anymore since that's the job of gfar_start(). Signed-off-by: Claudiu Manoil --- drivers/net/ethernet/freescale/gianfar.c | 53 ++++++++++++------------ drivers/net/ethernet/freescale/gianfar.h | 3 +- drivers/net/ethernet/freescale/gianfar_ethtool.c | 5 +-- 3 files changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c index 385de80..a2977a8 100644 --- a/drivers/net/ethernet/freescale/gianfar.c +++ b/drivers/net/ethernet/freescale/gianfar.c @@ -138,9 +138,7 @@ int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int amount_pull, struct napi_struct *napi); -void gfar_halt(struct net_device *dev); -static void gfar_halt_nodisable(struct net_device *dev); -void gfar_start(struct net_device *dev); +static void gfar_halt_nodisable(struct gfar_private *priv); static void gfar_clear_exact_match(struct net_device *dev); static void gfar_set_mac_for_addr(struct net_device *dev, int num, const u8 *addr); @@ -1070,10 +1068,6 @@ static void gfar_hw_init(struct gfar_private *priv) /* Program the interrupt steering regs, only for MG devices */ if (priv->num_grps > 1) gfar_write_isrg(priv); - - /* Enable all Rx/Tx queues after MAC reset */ - gfar_write(®s->rqueue, priv->rqueue); - gfar_write(®s->tqueue, priv->tqueue); } static void __init gfar_init_addr_hash_table(struct gfar_private *priv) @@ -1146,7 +1140,7 @@ static int gfar_probe(struct platform_device *ofdev) /* Stop the DMA engine now, in case it was running before * (The firmware could have used it, and left it running). */ - gfar_halt(dev); + gfar_halt(priv); gfar_hw_init(priv); @@ -1314,7 +1308,7 @@ static int gfar_suspend(struct device *dev) lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt_nodisable(ndev); + gfar_halt_nodisable(priv); /* Disable Tx, and Rx if wake-on-LAN is disabled. */ tempval = gfar_read(®s->maccfg1); @@ -1378,7 +1372,7 @@ static int gfar_resume(struct device *dev) tempval &= ~MACCFG2_MPEN; gfar_write(®s->maccfg2, tempval); - gfar_start(ndev); + gfar_start(priv); unlock_rx_qs(priv); unlock_tx_qs(priv); @@ -1410,7 +1404,7 @@ static int gfar_restore(struct device *dev) init_registers(ndev); gfar_set_mac_address(ndev); gfar_init_mac(ndev); - gfar_start(ndev); + gfar_start(priv); priv->oldlink = 0; priv->oldspeed = 0; @@ -1633,9 +1627,8 @@ static int __gfar_is_rx_idle(struct gfar_private *priv) } /* Halt the receive and transmit queues */ -static void gfar_halt_nodisable(struct net_device *dev) +static void gfar_halt_nodisable(struct gfar_private *priv) { - struct gfar_private *priv = netdev_priv(dev); struct gfar __iomem *regs = priv->gfargrp[0].regs; u32 tempval; @@ -1661,15 +1654,20 @@ static void gfar_halt_nodisable(struct net_device *dev) } /* Halt the receive and transmit queues */ -void gfar_halt(struct net_device *dev) +void gfar_halt(struct gfar_private *priv) { - struct gfar_private *priv = netdev_priv(dev); struct gfar __iomem *regs = priv->gfargrp[0].regs; u32 tempval; - gfar_halt_nodisable(dev); + /* Dissable the Rx/Tx hw queues */ + gfar_write(®s->rqueue, 0); + gfar_write(®s->tqueue, 0); - /* Disable Rx and Tx */ + mdelay(10); + + gfar_halt_nodisable(priv); + + /* Disable Rx/Tx DMA */ tempval = gfar_read(®s->maccfg1); tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); gfar_write(®s->maccfg1, tempval); @@ -1696,7 +1694,7 @@ void stop_gfar(struct net_device *dev) lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt(dev); + gfar_halt(priv); unlock_rx_qs(priv); unlock_tx_qs(priv); @@ -1801,17 +1799,15 @@ static void free_skb_resources(struct gfar_private *priv) priv->tx_queue[0]->tx_bd_dma_base); } -void gfar_start(struct net_device *dev) +void gfar_start(struct gfar_private *priv) { - struct gfar_private *priv = netdev_priv(dev); struct gfar __iomem *regs = priv->gfargrp[0].regs; u32 tempval; int i = 0; - /* Enable Rx and Tx in MACCFG1 */ - tempval = gfar_read(®s->maccfg1); - tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); - gfar_write(®s->maccfg1, tempval); + /* Enable Rx/Tx hw queues */ + gfar_write(®s->rqueue, priv->rqueue); + gfar_write(®s->tqueue, priv->tqueue); /* Initialize DMACTRL to have WWR and WOP */ tempval = gfar_read(®s->dmactrl); @@ -1830,9 +1826,14 @@ void gfar_start(struct net_device *dev) gfar_write(®s->rstat, priv->gfargrp[i].rstat); } + /* Enable Rx/Tx DMA */ + tempval = gfar_read(®s->maccfg1); + tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); + gfar_write(®s->maccfg1, tempval); + gfar_ints_enable(priv); - dev->trans_start = jiffies; /* prevent tx timeout */ + priv->ndev->trans_start = jiffies; /* prevent tx timeout */ } static void gfar_configure_coalescing(struct gfar_private *priv, @@ -1956,7 +1957,7 @@ int startup_gfar(struct net_device *ndev) } /* Start the controller */ - gfar_start(ndev); + gfar_start(priv); phy_start(priv->phydev); diff --git a/drivers/net/ethernet/freescale/gianfar.h b/drivers/net/ethernet/freescale/gianfar.h index 53e3466..2a59398 100644 --- a/drivers/net/ethernet/freescale/gianfar.h +++ b/drivers/net/ethernet/freescale/gianfar.h @@ -1205,7 +1205,8 @@ void unlock_tx_qs(struct gfar_private *priv); irqreturn_t gfar_receive(int irq, void *dev_id); int startup_gfar(struct net_device *dev); void stop_gfar(struct net_device *dev); -void gfar_halt(struct net_device *dev); +void gfar_halt(struct gfar_private *priv); +void gfar_start(struct gfar_private *priv); void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable, u32 regnum, u32 read); void gfar_configure_coalescing_all(struct gfar_private *priv); diff --git a/drivers/net/ethernet/freescale/gianfar_ethtool.c b/drivers/net/ethernet/freescale/gianfar_ethtool.c index 63d2344..69fab72 100644 --- a/drivers/net/ethernet/freescale/gianfar_ethtool.c +++ b/drivers/net/ethernet/freescale/gianfar_ethtool.c @@ -44,7 +44,6 @@ #include "gianfar.h" -extern void gfar_start(struct net_device *dev); extern int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); @@ -504,7 +503,7 @@ static int gfar_sringparam(struct net_device *dev, lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt(dev); + gfar_halt(priv); unlock_rx_qs(priv); unlock_tx_qs(priv); @@ -627,7 +626,7 @@ int gfar_set_features(struct net_device *dev, netdev_features_t features) lock_tx_qs(priv); lock_rx_qs(priv); - gfar_halt(dev); + gfar_halt(priv); unlock_tx_qs(priv); unlock_rx_qs(priv);