From patchwork Thu May 23 12:30:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 245942 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BB19B2C02A4 for ; Thu, 23 May 2013 22:29:57 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758926Ab3EWM3z (ORCPT ); Thu, 23 May 2013 08:29:55 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:39555 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758908Ab3EWM3x (ORCPT ); Thu, 23 May 2013 08:29:53 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r4NCTmHx016432; Thu, 23 May 2013 07:29:48 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r4NCTmmP016302; Thu, 23 May 2013 07:29:48 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Thu, 23 May 2013 07:29:48 -0500 Received: from a0131834-linux.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r4NCTTTm001517; Thu, 23 May 2013 07:29:46 -0500 From: Mugunthan V N To: CC: , , , , , Mugunthan V N Subject: [net-next PATCH v2 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM Date: Thu, 23 May 2013 18:00:28 +0530 Message-ID: <1369312228-3308-7-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369312228-3308-1-git-send-email-mugunthanvnm@ti.com> References: <1369312228-3308-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Todo: - if an idle state is available for pins, add support for it. Signed-off-by: Mugunthan V N --- arch/arm/boot/dts/am335x-evm.dts | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 0423298..beb2fbf 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -44,6 +44,32 @@ 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */ >; }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2 | OUTPUT */ + 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2 | INPUT_PULLDOWN */ + 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2 | OUTPUT */ + 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2 | OUTPUT */ + 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2 | OUTPUT */ + 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2 | OUTPUT */ + 0x12c 0x2 /* mii1_txclk.rgmii1_tclk, MODE2 | OUTPUT */ + 0x130 0x22 /* mii1_rxclk.rgmii1_rclk, MODE2 | INPUT_PULLDOWN */ + 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2 | INPUT_PULLDOWN */ + 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2 | INPUT_PULLDOWN */ + 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2 | INPUT_PULLDOWN */ + 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2 | INPUT_PULLDOWN */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 0x30 /* mdio_data.mdio_data, MODE0 | INPUT_PULLUP */ + 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 | OUTPUT_PULLUP */ + >; + }; }; ocp { @@ -237,6 +263,16 @@ }; }; +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; +}; + &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; };