From patchwork Fri May 3 07:38:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 241241 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9C2392C0163 for ; Fri, 3 May 2013 17:39:35 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933091Ab3ECHjb (ORCPT ); Fri, 3 May 2013 03:39:31 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33102 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933080Ab3ECHja (ORCPT ); Fri, 3 May 2013 03:39:30 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r437dPGx018142; Fri, 3 May 2013 02:39:25 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r437dPCK021744; Fri, 3 May 2013 02:39:25 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Fri, 3 May 2013 02:39:25 -0500 Received: from psplinux063.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r437d5w6004833; Fri, 3 May 2013 02:39:23 -0500 From: Mugunthan V N To: CC: , , , , , Mugunthan V N Subject: [net-next PATCH 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM Date: Fri, 3 May 2013 13:08:56 +0530 Message-ID: <1367566736-26644-7-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1367566736-26644-1-git-send-email-mugunthanvnm@ti.com> References: <1367566736-26644-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Todo: - if an idle state is available for pins, add support for it. Signed-off-by: Mugunthan V N --- arch/arm/boot/dts/am335x-evm.dts | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index d649644..e7f91e8 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -44,6 +44,32 @@ 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */ >; }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2 | OUTPUT */ + 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2 | INPUT_PULLDOWN */ + 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2 | OUTPUT */ + 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2 | OUTPUT */ + 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2 | OUTPUT */ + 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2 | OUTPUT */ + 0x12c 0x2 /* mii1_txclk.rgmii1_tclk, MODE2 | OUTPUT */ + 0x130 0x22 /* mii1_rxclk.rgmii1_rclk, MODE2 | INPUT_PULLDOWN */ + 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2 | INPUT_PULLDOWN */ + 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2 | INPUT_PULLDOWN */ + 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2 | INPUT_PULLDOWN */ + 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2 | INPUT_PULLDOWN */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 0x30 /* mdio_data.mdio_data, MODE0 | INPUT_PULLUP */ + 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 | OUTPUT_PULLUP */ + >; + }; }; ocp { @@ -237,6 +263,16 @@ }; }; +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; +}; + &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; };